X-Authentication-Warning: delorie.com: mail set sender to geda-user-bounces using -f X-Recipient: geda-user AT delorie DOT com X-TCPREMOTEIP: 207.224.51.38 X-Authenticated-UID: jpd AT noqsi DOT com From: John Doty Content-Type: multipart/alternative; boundary="Apple-Mail=_2ADC1C49-9637-44C9-BE5F-68EA9D98A931" Message-Id: <3C8720CE-BCBC-460A-9EE2-5A2BCE57C0F7@noqsi.com> Mime-Version: 1.0 (Mac OS X Mail 7.3 \(1878.6\)) Subject: Re: [geda-user] FOSDEM Date: Fri, 6 Feb 2015 13:00:17 -0700 References: <1420499386 DOT 3521 DOT 3 DOT camel AT cam DOT ac DOT uk> <20150202152654 DOT GA13336 AT cuci DOT nl> <54CFD589 DOT 9040702 AT xs4all DOT nl> <20150203112631 DOT 3507a0c1 AT Parasomnia DOT thuis DOT lan> <20150204054256 DOT Horde DOT Pm1JV8RJbICk9SHvIGwZ7A3 AT webmail DOT in-berlin DOT de> <20150204193720 DOT Horde DOT 42xUN-NzhCJRWZne-M5eCQ1 AT webmail DOT in-berlin DOT de> <90236728-E79D-47C7-BFB1-34140DB85ACB AT sbcglobal DOT net> <201502042333 DOT t14NX28o024789 AT envy DOT delorie DOT com> <7C1A5871-3056-482C-BC58-173D90D80F77 AT icloud DOT com> To: geda-user AT delorie DOT com In-Reply-To: X-Mailer: Apple Mail (2.1878.6) Reply-To: geda-user AT delorie DOT com Errors-To: nobody AT delorie DOT com X-Mailing-List: geda-user AT delorie DOT com X-Unsubscribes-To: listserv AT delorie DOT com Precedence: bulk --Apple-Mail=_2ADC1C49-9637-44C9-BE5F-68EA9D98A931 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=windows-1252 On Feb 6, 2015, at 11:47 AM, Ouabache Designworks = wrote: > I do hope that you keep it flexible enough to extend down into = asic/fpgas or up into multiboard product design.=20 Simulation. Symbolic circuit analysis. Automatic documentation generation. Import/export of design data from/to other tools. For an example of the last, right now I=92m working with an FPGA = designer and a printer circuit board designer. I do the mixed signal = engineering and schematic capture part with gEDA. I also simulate the = analog blocks (gnet-spice-noqsi and ngspice). The FPGA designer exports = a .csv file of pin numbers, names and characteristics from her Xilinx = tools. I have a file that relates pin names to net names. I grind those = through a simple AWK script that generates a file of pin number to net = name relations, and then grind that through pins2gsch. Gnetlist then = merges that with other pin maps and schematic data, producing an Allegro = netlist for the board designer. Try doing that kind of collaborative = work with KiCad. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ jpd AT noqsi DOT com --Apple-Mail=_2ADC1C49-9637-44C9-BE5F-68EA9D98A931 Content-Transfer-Encoding: quoted-printable Content-Type: text/html; charset=windows-1252
On Feb 6, 2015, at 11:47 AM, Ouabache = Designworks <z3qmtr45 AT gmail DOT com> = wrote:

I do hope that you keep it flexible = enough to extend down into asic/fpgas or up into multiboard product = design. 
Simulation.

Symbolic circuit = analysis.

Automatic documentation = generation.

Import/export of design data = from/to other tools.

For an example of the = last, right now I=92m working with an FPGA designer and a printer = circuit board designer. I do the mixed signal engineering and schematic = capture part with gEDA. I also simulate the analog blocks = (gnet-spice-noqsi and ngspice). The FPGA designer exports a .csv file of = pin numbers, names and characteristics from her Xilinx tools. I have a = file that relates pin names to net names. I grind those through a simple = AWK script that generates a file of pin number to net name relations, = and then grind that through pins2gsch. Gnetlist then merges that with = other pin maps and schematic data, producing an Allegro netlist for the = board designer. Try doing that kind of collaborative work with = KiCad.

John Doty              Noqsi = Aerospace, Ltd.

http://www.noqsi.com/

jpd AT noqsi DOT com

= --Apple-Mail=_2ADC1C49-9637-44C9-BE5F-68EA9D98A931--