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On Tue, Feb 3, 2015 at 10:37 PM, Hagen SANKOWSKI <hsank AT nospam DOT chipforge DOT org
> wrote:


>  If we could get all the eda teams currently supporting their own tool
>> flows
>> to contribute to a single open source solution then we would all be a lot
>> better off.
>>
>
> Well, everybody has it's own solution. With own pit falls, with own
> advantages.
>

With  open source tool flows you can donate code that demonstrates your
advantages so
that other designers with clumsier code can try out yours and switch over
if they like.


 We got to start talking to each other and sharing ideals and problems.
>> There is no money in this for Big EDA so don't expect any help from them
>> but we need this. This could be the "Linux" of the EDA world.
>>
>
> So, which requirements do you/we have?
>
>

I want the architects to be able to enter the block diagram of an entire
system  in schematic form.  The team can then take this and identify which
blocks map to real parts (drams, drivers etc) and which ones go into an
Digital chip. The emulation team can identify multiple FPGAs while the asic
team only identifies their asic. Both teams work from the same source so
that any changes are effective in both.

Anything not identified as inside of a Digital chip is a real  part mounted
on a PCB. You can autogenerate the symbols for all digital chips and dump
out separate netlists for the PCB and all the digital chips.

You can identify any nodes for Signal Integrity checks and extract a spice
model of the PCB traces along with IBIS models of the drivers.

John Eaton

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Content-Type: text/html; charset=UTF-8
Content-Transfer-Encoding: quoted-printable

<div dir=3D"ltr"><br><div class=3D"gmail_extra"><br><div class=3D"gmail_quo=
te">On Tue, Feb 3, 2015 at 10:37 PM, Hagen SANKOWSKI <span dir=3D"ltr">&lt;=
<a href=3D"mailto:hsank AT nospam DOT chipforge DOT org" target=3D"_blank">hsank AT nospa=
m.chipforge.org</a>&gt;</span> wrote:<br><br><blockquote class=3D"gmail_quo=
te" style=3D"margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"=
><span class=3D""><br>
<blockquote class=3D"gmail_quote" style=3D"margin:0 0 0 .8ex;border-left:1p=
x #ccc solid;padding-left:1ex">
If we could get all the eda teams currently supporting their own tool flows=
<br>
to contribute to a single open source solution then we would all be a lot<b=
r>
better off.<br>
</blockquote>
<br></span>
Well, everybody has it&#39;s own solution. With own pit falls, with own adv=
antages.<span class=3D""><br></span></blockquote><div><br></div><div>With=
=C2=A0 open source tool flows you can donate code that demonstrates your ad=
vantages so<br></div><div>that other designers with clumsier code can try o=
ut yours and switch over if they like.<br></div><div><br>
<br>
</div><blockquote class=3D"gmail_quote" style=3D"margin:0 0 0 .8ex;border-l=
eft:1px #ccc solid;padding-left:1ex"><span class=3D""><blockquote class=3D"=
gmail_quote" style=3D"margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-=
left:1ex">
We got to start talking to each other and sharing ideals and problems.<br>
There is no money in this for Big EDA so don&#39;t expect any help from the=
m<br>
but we need this. This could be the &quot;Linux&quot; of the EDA world.<br>
</blockquote>
<br></span>
So, which requirements do you/we have?<br><div class=3D"HOEnZb"><div class=
=3D"h5">
<br></div></div></blockquote><div><br><br></div><div>I want the architects =
to be able to enter the block diagram of an entire system=C2=A0 in schemati=
c form.=C2=A0 The team can then take this and identify which blocks map to =
real parts (drams, drivers etc) and which ones go into an Digital chip. The=
 emulation team can identify multiple FPGAs while the asic team only identi=
fies their asic. Both teams work from the same source so that any changes a=
re effective in both.<br><br></div><div>Anything not identified as inside o=
f a Digital chip is a real=C2=A0 part mounted on a PCB. You can autogenerat=
e the symbols for all digital chips and dump out separate netlists for the =
PCB and all the digital chips. <br><br></div><div>You can identify any node=
s for Signal Integrity checks and extract a spice model of the PCB traces a=
long with IBIS models of the drivers.<br><br></div><div>John Eaton<br><br>=
=C2=A0<br></div><div><br>=C2=A0</div></div></div></div>

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