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Date: Tue, 20 Jan 2015 20:45:46 +0100
From: Florian Teply <usenet AT teply DOT info>
To: geda-user AT delorie DOT com
Subject: Re: [geda-user] HIDDEN PINS IN A SYMBOL
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Am Sun, 18 Jan 2015 13:58:27 -0500
schrieb DJ Delorie <dj AT delorie DOT com>:

> 
> > Slightly not directly related to symbols, but it always sstrikes me
> > as odd that some (actually most for that kind of part) manufacturers
> > decide to use four pins for the drain, but only one for the source
> > terminal.
> 
> I always assumed the drain was on the bottom of the wafer, and that
> the extra pins were for heat dissipation...  The OnSemi app note
> for their ChipFET line say:
> 
>  "The pin–out is similar to the TSOP–6 configuration, with two
>   additional drain pins to enhance power dissipation and thermal
>   performance."
> 
> The ST smd app note says this about their SO-8 package:
> 
>  "Since the drain pins serve the additional function of providing the
>   thermal connection to the package, . . ."
> 
> See also:
> http://electronics.stackexchange.com/questions/32511/why-so-many-pins-for-the-mosfets-drain

I knew I was missing something. Working in a small SiGe BiCMOS fab, I
didn't think about vertical MOSFETs or anything less than twin-well
processes for that matter. An in these kind of processes, all drains
are isolated from the substrate by at least one reverse-biased
junction...

Thanks for pointing in the right direction,
Florian