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Date: Thu, 17 Jul 2014 02:11:32 +0200
From: Bernd Walter <ticso AT cicely7 DOT cicely DOT de>
To: geda-user AT delorie DOT com
Subject: Re: [geda-user] opper ring flag for vias and pins
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On Wed, Jul 16, 2014 at 02:22:50PM -0400, DJ Delorie wrote:
> 
> > You need to be able to remove inner layer pad annuli completely for 
> > signal integrity reasons on some high-speed lines.
> 
> Aren't there manufacturability issues if you do that?  I.e. voids
> where the copper should be, causing breaks in the barrel?

Why should there be any?
I can't tell for sure, but when the holes are drilled and plated after
stacking then such a plated hole without inside annular rings should
be just the same as they would be with a standard 2-layer board.
But I just investigated some very high densisty CPU boards I had
within reach and all of them used microvias, but had at least rings
on the outside layers of all vias.
I probably should ask a board manufacturer about their opinions.

-- 
B.Walter <bernd AT bwct DOT de> http://www.bwct.de
Modbus/TCP Ethernet I/O Baugruppen, ARM basierte FreeBSD Rechner uvm.