X-Authentication-Warning: delorie.com: mail set sender to geda-user-bounces using -f X-Recipient: geda-user AT delorie DOT com Message-ID: <53C56BEB.7030701@sonic.net> Date: Tue, 15 Jul 2014 10:59:07 -0700 From: Dave Curtis User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:16.0) Gecko/20121028 Thunderbird/16.0.2 MIME-Version: 1.0 To: geda-user AT delorie DOT com Subject: Re: [geda-user] opper ring flag for vias and pins References: <20140715173322 DOT GC56151 AT cicely7 DOT cicely DOT de> In-Reply-To: <20140715173322.GC56151@cicely7.cicely.de> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Sonic-ID: C;UGcyt0kM5BGiS02zUc16mQ== M;ypZMt0kM5BGiS02zUc16mQ== X-Spam-Flag: No X-Sonic-Spam-Details: 0.0/5.0 by cerberusd Reply-To: geda-user AT delorie DOT com On 07/15/2014 10:33 AM, Bernd Walter wrote: > Because I just remember this, while I wrote about holes and multilayer. > I would love to selectively switch of the copper ring per layer on > vias and pins. > The reason is that I only need to ring on solder side and on connecting > layers. > On layers I don't need the ring it just reduces space, especially > problematic with a via field e.g. inside a BGA. > It is not just routing space - the wider space between vias and pins > are preferable for groundplanes too. > So one thing I thought of that might help: Set the pad diameter on the Pin[] to the small diameter that you want on the inner layers. Larger pads cans be had on comp and solder side by drawing coincident Pad[] elements with the same pin number.