X-Authentication-Warning: delorie.com: mail set sender to geda-user-bounces using -f Date: Wed, 9 Jul 2014 18:23:00 -0400 Message-Id: <201407092223.s69MN0iE000952@envy.delorie.com> From: DJ Delorie To: geda-user AT delorie DOT com In-reply-to: <53BDBC7A.5070709@sonic.net> (message from Dave Curtis on Wed, 09 Jul 2014 15:04:42 -0700) Subject: Re: [geda-user] pour clearing around pads References: <201407091750 DOT s69HofTL021912 AT envy DOT delorie DOT com> <53BDBC7A DOT 5070709 AT sonic DOT net> Reply-To: geda-user AT delorie DOT com Errors-To: nobody AT delorie DOT com X-Mailing-List: geda-user AT delorie DOT com X-Unsubscribes-To: listserv AT delorie DOT com Precedence: bulk > > * board-level fill > > * board-level cut > > * footprint-level fill > > * footprint-level cut > > * traces > I agree with all that. The need for a footprint-level version of the > layers distinct from the lay-out level isn't extremely clear for me, but > I assume that makes internal operations easier to sort out. It doesn't need to be footprint-vs-layout, it's just that there needs to be rules about how to apply layered patterns when recursively defining layouts in terms of sub-layouts and/or footprints. I.e. the above list is, internally, simply: * positive, polygons, lines, etc * negative, polygons, lines, etc * sub-part (from footprint, sub-layout, whatever) * positive, etc * negative, etc * positive, etc * positive, etc > And what are the chances of this happening in pcb? Is that a doable > change? Someone would have to have the drive and time to do it. I think it's a fundamental change to the pcb internals, which means it touches most of the code. > So here is another one. I saw my KiCad-using friend (at the "Wednesday In some EDA packages, the footprint includes some "skyscraper" information that gives a rough idea of space needed in 3-D terms. Sometimes that info can be used to do a 3-D model of the layout, sometimes that info is used as a 3-D "keep out". We could define a type of that data that means "remove board here" but I'm not sure how well that would relate to the rest of PCB. I mean, lots of places in pcb need to know the "shape of the board". Now we're adding "shape of the board from layer X to layer Y" etc. How much of this shape will be dynamically computed by scanning the layout? How much will be pre-computed and cached? How will this affect performance or code readability? I don't know the answers to those questions.