X-Authentication-Warning: delorie.com: mail set sender to geda-user-bounces using -f X-Recipient: geda-user AT delorie DOT com X-CT-Class: Clean X-CT-Score: 0.00 X-CT-RefID: str=0001.0A020205.53B8D921.0017,ss=1,re=0.000,fgs=0 X-CT-Spam: 0 X-Authority-Analysis: v=2.0 cv=fKfnK+me c=1 sm=1 a=/h2QNzLQAzIfywEVN7Z3Gw==:17 a=tJMfm19-yuMA:10 a=G8Uczd0VNMoA:10 a=kj9zAlcOel0A:10 a=kviXuzpPAAAA:8 a=npWvucpvR0Rz5-WkoboA:9 a=CjuIK1q_8ugA:10 a=/h2QNzLQAzIfywEVN7Z3Gw==:117 X-CM-Score: 0.00 Authentication-Results: cox.net; auth=pass (PLAIN) smtp.auth=ebrombaugh1 AT cox DOT net Subject: Re: [geda-user] pour clearing around pads Mime-Version: 1.0 (Apple Message framework v1085) Content-Type: text/plain; charset=us-ascii From: Eric Brombaugh In-Reply-To: Date: Sat, 5 Jul 2014 22:05:36 -0700 Message-Id: <33C09B4F-1D7D-494E-8564-720B4C7F580A@cox.net> References: To: geda-user AT delorie DOT com X-Mailer: Apple Mail (2.1085) Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by delorie.com id s6655gxn028519 Reply-To: geda-user AT delorie DOT com Errors-To: nobody AT delorie DOT com X-Mailing-List: geda-user AT delorie DOT com X-Unsubscribes-To: listserv AT delorie DOT com Precedence: bulk On Jul 5, 2014, at 9:11 PM, Dave Curtis wrote: > I'm working on a footprint where if I follow the data-sheet geometry and my normal design rules, I end up with a footprint where very skinny copper peninsulas sneak between pads when it is placed in a polygon. The peninsulas neck down to less than the minimum copper width rule. > > So, first off, I'm surprised that the Cu polygon allows Cu to pour into a space less than the minimum width rule. > > Secondly, I'm wondering if fab houses might flag that as a DRC violation even if pcb doesn't. This has been a problem with PCB poly fill for as long as I've been using it. I've never had a fab house complain about it, but I have had boards come back with shorts due to the thin copper fingers lifting and drifting around under the mask. PCB's poly fill algorithm is generally a disaster - it leaves large regions unfilled if there are intervening traces and pads, often crashes the application when used in complex geometries and as seen above results in significant DRC violations. The only way around this is to carefully subdivide the polygons into smaller regions by hand in order to work around the blockages, but that results in designs with dozens if not hundreds of small polygons that become difficult to maintain. Other FOSS pcb design tools seem to handle this function more gracefully - see how KiCAD does it for example. Having vented, I would note that I'm a fan of PCB and I continue to use it happily despite this wart. I suppose if it bothered me enough I'd make the effort to understand how this works and try to fix it, but there always seems to be something more fun to do. Eric