X-Authentication-Warning: delorie.com: mail set sender to geda-user-bounces using -f X-Recipient: geda-user AT delorie DOT com X-Envelope-From: paubert AT iram DOT es Date: Mon, 28 Oct 2013 10:03:09 +0100 From: Gabriel Paubert To: geda-user AT delorie DOT com Subject: Re: [geda-user] Power to ICs with numslots > 1 Message-ID: <20131028090308.GA9225@visitor2.iram.es> References: <201310261908 DOT r9QJ8Vv8025803 AT envy DOT delorie DOT com> <526C9628 DOT 7000201 AT sonic DOT net> <1382899880 DOT 21120 DOT 7 DOT camel AT pcjc2lap> <526DB865 DOT 1040200 AT ecosensory DOT com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <526DB865.1040200@ecosensory.com> User-Agent: Mutt/1.5.20 (2009-06-14) X-Spamina-Bogosity: Unsure X-Spamina-Spam-Score: -0.5 (/) X-Spamina-Spam-Report: Content analysis details: (-0.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -1.0 ALL_TRUSTED Passed through trusted hosts only via SMTP 0.5 DATE_IN_PAST_24_48 Date: is 24 to 48 hours before Received: date Reply-To: geda-user AT delorie DOT com Errors-To: nobody AT delorie DOT com X-Mailing-List: geda-user AT delorie DOT com X-Unsubscribes-To: listserv AT delorie DOT com Precedence: bulk On Sun, Oct 27, 2013 at 08:05:41PM -0500, John Griessen wrote: > On 10/27/2013 01:51 PM, Peter Clifton wrote: > >IMO, connecting the hierarchy explicitly is superior (and less prone to > >errors) than trying to use flat net-names across the whole design. > > Yes, me too, and that matches my old chip design experience, where reusing a block never depended > on names internal to it. (I mention chip design because it is very virtual/nit-picky and > mistakes in physical chips very expensive). Chip design is very different from PCB design. I've never designed a chip (I'd like to), but on a PCB I want: a) short refdes so that I can fit as many as possible on a PCB. I don't really mind hiding the reference designators of decoupling caps, but I hate hiding them on anything else. b) that the refdes on the PCB match what is on the schematics, so renaming them in the netlisting phase is excluded. This obviously prevents putting several instances of the same schematics, but I've found it to be the lesser of 2 evils. c) when I have even a moderately sized FPGA, the part is split into many symbols, in the last design it was split into 9 symbols spread over 6 pages and of course they all have the same refdes. (What's missing in gEDA is a tool to renumber such parts). This is a small FPGA for today's standards (256 pins), with large ones (over 1500 pins) you probably need to create several symbols only for power supplies. Basically these two conditions mean that I use global names for refdeses and at least power nets (there are not so many, and I'd hate to have to explicitly connect S1/GND with S2/GND and so on). This is also what the person to which I subcontract layouts prefers. However, when I write code for an FPGA, typically in VHDL, I have no problem with long, hierachical names, coming out of the processes (simulation and synthesis), which also simplify reuse of modules. Bottom line, one size fits all does not work! gEDA (gnetlist in this case) gives you the choice, fortunately. Regards, Gabriel