X-Authentication-Warning: delorie.com: mail set sender to geda-user-bounces using -f X-Recipient: geda-user AT delorie DOT com X-EIP: [Q7YVLu8nFfFav3GeogUVs2LUrebKyy0/] X-Originating-Email: [hdlguy AT hotmail DOT com] Message-ID: Content-Type: multipart/alternative; boundary="_ac8d6ce6-6161-4470-a3fd-f8afd7e6456d_" From: peter dudley To: Subject: RE: [geda-user] PHDL to PCB conversion path? Date: Fri, 8 Mar 2013 06:43:44 -0700 Importance: Normal In-Reply-To: <5139E570.9060509@laserlinc.com> References: <3B7337D3-C547-42A5-8480-38379A3EB076 AT noqsi DOT com>,<5139E570 DOT 9060509 AT laserlinc DOT com> MIME-Version: 1.0 X-OriginalArrivalTime: 08 Mar 2013 13:43:45.0679 (UTC) FILETIME=[F46F99F0:01CE1C02] Reply-To: geda-user AT delorie DOT com Errors-To: nobody AT delorie DOT com X-Mailing-List: geda-user AT delorie DOT com X-Unsubscribes-To: listserv AT delorie DOT com Precedence: bulk --_ac8d6ce6-6161-4470-a3fd-f8afd7e6456d_ Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Josh=2C Thank you for your reply (and to others who replied earlier). Your suggestion is interesting. Honestly=2C one of our goals has always be= en to have a way to graphically review the PHDL design. Writing the gEDA s= chematic file would be one way to accomplish that. Your tagging idea would allow the user to pretty up their schematics while = incrementally adding to those schematics. New items would not mess up previ= ous edits to the schematics. Pete > Date: Fri=2C 8 Mar 2013 08:19:44 -0500 > From: Joshua DOT Lansford AT laserlinc DOT com > To: geda-user AT delorie DOT com > Subject: Re: [geda-user] PHDL to PCB conversion path? >=20 >=20 > On 03/07/2013 10:37 PM=2C John Doty wrote: > >> Does it make sense for us to write gEDA schematic files? > > Quite possibly. While creating schematics with human-readable graphics = is an AI problem=2C schematics that gnetlist can handle are much easier. Se= ehttp://www.gedasymbols.org/user/john_doty/tools/pins2gsch.html >=20 > Here is a fun idea: When you generate the schematic file=2C tag each=20 > component with an id. (gschem allows custom tags) Then when you export= =20 > again=2C any components and connections that already exist can stay where= =20 > they are and only the difference in wiring and components would be added= =20 > which would then be adjusted by hand. All graphical decoration stuff=20 > could be left alone. > This would allow folks to iteratively complete their design using PHDL=20 > as the foundation and graphically place the symbols. Just as it helps=20 > to make a schematic before making a pcb layout=2C it would help to make a= =20 > PHDL design before making a schematic. Thus the relationship between=20 > the first two probably would apply to the second. Just a higher=2C more= =20 > powerful abstraction level. This would give the users of PHDL the added=20 > bonus of having a graphical representation to double check that their=20 > language use is correct as well as something to give the layout folks=20 > with the netlist if they are not going to do the layout themselves. >=20 > Just my 2 cents. :-) Someone had to mention this idea. It was begging= =20 > to be brought up. > ~Joshua = --_ac8d6ce6-6161-4470-a3fd-f8afd7e6456d_ Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable

Josh=2C

Thank you for your reply (and to others who replied earlier)= .

Your suggestion is interesting. =3B Honestly=2C one of our goa= ls has always been to have a way to graphically review the PHDL design.&nbs= p=3B Writing the gEDA schematic file would be one way to accomplish that.
Your tagging idea would allow the user to pretty up their schematics = while incrementally adding to those schematics. New items would not mess up= previous edits to the schematics.

=3B Pete

>=3B Date: Fri=2C 8 Mar 2013 08:19:44 -050= 0
>=3B From: Joshua DOT Lansford AT laserlinc DOT com
>=3B To: geda-user AT del= orie.com
>=3B Subject: Re: [geda-user] PHDL to PCB conversion path?>=3B
>=3B
>=3B On 03/07/2013 10:37 PM=2C John Doty wrote:>=3B >=3B>=3B Does it make sense for us to write gEDA schematic fi= les?
>=3B >=3B Quite possibly. While creating schematics with human-= readable graphics is an AI problem=2C schematics that gnetlist can handle a= re much easier. Seehttp://www.gedasymbols.org/user/john_doty/tools/pins2gsc= h.html
>=3B
>=3B Here is a fun idea: When you generate the sche= matic file=2C tag each
>=3B component with an id. (gschem allows cus= tom tags) Then when you export
>=3B again=2C any components and conn= ections that already exist can stay where
>=3B they are and only the = difference in wiring and components would be added
>=3B which would t= hen be adjusted by hand. All graphical decoration stuff
>=3B could b= e left alone.
>=3B This would allow folks to iteratively complete thei= r design using PHDL
>=3B as the foundation and graphically place the = symbols. Just as it helps
>=3B to make a schematic before making a p= cb layout=2C it would help to make a
>=3B PHDL design before making a= schematic. Thus the relationship between
>=3B the first two probabl= y would apply to the second. Just a higher=2C more
>=3B powerful abs= traction level. This would give the users of PHDL the added
>=3B bonu= s of having a graphical representation to double check that their
>= =3B language use is correct as well as something to give the layout folks <= br>>=3B with the netlist if they are not going to do the layout themselve= s.
>=3B
>=3B Just my 2 cents. :-) Someone had to mention this = idea. It was begging
>=3B to be brought up.
>=3B ~Joshua

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