X-Authentication-Warning: delorie.com: mail set sender to geda-user-bounces using -f
X-Recipient: geda-user AT delorie DOT com
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
        d=gmail.com; s=20120113;
        h=mime-version:in-reply-to:references:date:message-id:subject:from:to
         :content-type;
        bh=FSaloH/jRUwbWPKW6YVc+aCl0YEwGUN6Ea6QokZdLbs=;
        b=oPA0sBAM6T8rj52JGxXL/VStc5ngEaRlfhyMRhCWm5ix13iem6AMc6B5k/MUlbPAAN
         g1CkOpKdspGTdgtXzZwL2jYM3rf2hh6hkTKvEM9gEERA4grmU3Tl+3dOJXb8+qSXqx62
         IwcEu3pGQWG1gDpI4IOtlzxWe3hUFx4xZak0mipjPW2165QgNgE7ANqP+ubd6eLdBnxN
         X5oU+vk4tyvLDmVYKX21+t06wLc9psutxaMgCO/HvL3sW4mdJcEvOpWuV33/Nz7wS3Xe
         Ti0WiHPecFY0Xf3JCNYauBlOfjbiumiIzT88syRQrz1i2xEXfrNhp/XMLQgKvR2JCK1k
         Igsg==
MIME-Version: 1.0
In-Reply-To: <508888FE.30001@neurotica.com>
References: <1350863030 DOT 93187 DOT YahooMailNeo AT web121004 DOT mail DOT ne1 DOT yahoo DOT com>
	<k64ffs$653$1 AT ger DOT gmane DOT org>
	<50888773 DOT 5020403 AT icarus DOT com>
	<508888FE DOT 30001 AT neurotica DOT com>
Date: Thu, 25 Oct 2012 23:43:55 +0200
Message-ID: <CAGde_xOXs2QERjNA5oEhg5aBXiiN1+tZp1v6SQnJwc6QhC4okQ@mail.gmail.com>
Subject: Re: [geda-user] FPGA / CPLD development with Linux
From: Svenn Are Bjerkem <svenn DOT bjerkem AT googlemail DOT com>
To: geda-user AT delorie DOT com
Content-Type: text/plain; charset=ISO-8859-1
Reply-To: geda-user AT delorie DOT com
Errors-To: nobody AT delorie DOT com
X-Mailing-List: geda-user AT delorie DOT com
X-Unsubscribes-To: listserv AT delorie DOT com
Precedence: bulk

On 25 October 2012 02:34, Dave McGuire <mcguire AT neurotica DOT com> wrote:
> On 10/24/2012 08:27 PM, Stephen Williams wrote:
>> On 10/22/2012 02:57 PM, Kai-Martin Knaak wrote:
>>> I don't know. Since we are locatd in europe, we go the VHDL way
>>> ;-)
>>
>> For the record, I've been doing some sponsored work to add VHDL to
>> Icarus Verilog. It's pretty basic at this point, but the end goal
>> is mixed SystemVerilog/VHDL in Icarus Verilog. Woo hoo! (*whew*)
>
>   Nice!!

Just for the record, over at the alliance mailing list, I just learned
that a guy is writing a thesis using icarus verilog and a patched
plug-in for translating that verilog to vhdl to be able to pipe
through alliance VLSI. Seems he has been able to get his stuff through
as he was asking about block layout issues. That's a bit further down
the pipe than translating verilog -> vhdl.

Work has also been done to get ghdl up to date with the gcc compiler
used in newer Linux distributions, as that is kind of a showstopper
for ghdl for the time being.

-- 
Svenn