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Date: Wed, 24 Oct 2012 09:07:48 +1100
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Subject: Re: [geda-user] Trace width - best practices?
From: Stephen Ecob <stephen DOT ecob AT sioi DOT com DOT au>
To: geda-user AT delorie DOT com
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On Wed, Oct 24, 2012 at 6:24 AM, Jan Kasprzak <kas AT fi DOT muni DOT cz> wrote:
>         Hello,
>
> in my board, I want to have some connections built for higher currents.
> Is it possible to mark them somehow (maybe even at the schmatics level?),
> and then let the autorouter to do its work, or do they need to be routed
> manually?

That would be a nice feature, but PCB doesn't have it.
It has been discussed, but no one has implemented it yet.
Are you interested in hacking the code ? :)

> Note that I don't want the whole net to be made from wider traces,
> only connections between some of the pins of the same net should be made wider.

You'll need to route the wider portions manually.
I think you'll find it easier to do that  first and then let the
autorouter do the thinner traces.

>         In a related question: is it possible to include hints for routing
> and placement in the schematics? For example:
>
> - this decoupling capacitor should be placed as close to this chip as possible

Similarly: the idea is a good one, it has been suggested before, but
no one has coded it up.
IIRC gschem can add suitable attributes to nets, but PCB doesn't have
any code to act on net
attributes.

> - these four connections together form a current loop, and the loop as a whole
>         should be made as short as possible

That would be nice.  We could change the auto-placer to act on hints like that.
The current auto-placer is unfortunately very weak, the best thing
about it is that it acts as a place holder
waiting for someone to code up a usable auto placement algorithm.
I find the current simulated annealing placement algorithm to be
interesting to watch but not actually usable for real projects.

Stephen Ecob
Silicon On Inspiration
Sydney Australia
www.sioi.com.au