X-Authentication-Warning: delorie.com: mail set sender to geda-user-bounces using -f X-Recipient: geda-user AT delorie DOT com Date: Wed, 25 Jul 2012 14:34:18 -0700 From: Colin D Bennett To: geda-user AT delorie DOT com Subject: Re: [geda-user] how to use "clearance" and mask in pcb footprint Message-ID: <20120725143418.5f735b1d@svelte> In-Reply-To: <5010D52B.8030800@plastitar.com> References: <5010D52B DOT 8030800 AT plastitar DOT com> X-Mailer: Claws Mail 3.8.0 (GTK+ 2.24.10; x86_64-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - gator297.hostgator.com X-AntiAbuse: Original Domain - delorie.com X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - gibibit.com X-BWhitelist: no X-Source: X-Source-Args: X-Source-Dir: X-Source-Sender: (svelte) [65.61.115.34]:33278 X-Source-Auth: colin AT gibibit DOT com X-Email-Count: 2 X-Source-Cap: c2t5bGVuO3NreWxlbjtnYXRvcjI5Ny5ob3N0Z2F0b3IuY29t Reply-To: geda-user AT delorie DOT com Errors-To: nobody AT delorie DOT com X-Mailing-List: geda-user AT delorie DOT com X-Unsubscribes-To: listserv AT delorie DOT com Precedence: bulk On Thu, 26 Jul 2012 01:27:07 -0400 Phil Taylor wrote: > On 7/25/2012 12:05 PM, Ram Bhamidipaty wrote: > > I'm pretty sure the way I am doing the pins with the mask and > > clearance values is wrong. Are there some general rules I > > should follow for solder mask and clearance values? Are > > clearance and mask values dependent on the board fab rules? > > Ram, > > This document explains the clearance and mask numbers ... which > are not as obvious as you might at first think. > > The design rules in PCB do not modify file footprints. The > footprints are what they are ... when you write them. This would > pertain to text-written file type footprints. I have no idea > about footprints created in PCB's gui. The design rules in pcb aren't related to footprint clearance and mask settings, except that if the clearance to polygons is too small, it could violate design rules of a specific layout and cause a DRC error. Footprints created in pcb's GUI by drawing them will save mask/clearance settings based on the route style selected (e.g., Signal, Power, Fat, ...) unless you modify these mask/clearance settings first manually. The weird thing about mask and clearance is how they are specified: # Clearance: add to thickness to get clearance diameter # Mask: diameter of solder mask opening This means for example if you have a 20 mil wide pad (think of it as a LINE, since that's what it is), and you want 12 mil clearance to polygons with 3 mil gap from solder mask to copper, set the following **in the .fp footprint file** (not using pcb GUI, since it uses a different scheme!!) thickness = 20mil # Note: copper "diameter" clearance = 2 * 12mil = 24mil # Note: just the diameter increment mask = 20mil + (2 * 3mil) = 26mil # Note: total diameter Like this: Element["" "" "" "" 1430.00mil 1860.00mil 0.0000 0.0000 0 44 ""] ( # ------------------------------------------------------------------ # Pad[ rX1 rY1 rX2 rY2 Thickn Clr Msk Nm Nr Fl] # ------------------------------------------------------------------ Pad[-110.00mil 0.0000 60.00mil 0.0000 20.00mil 24.00mil 26.00mil "1" "1" ""] # Pad 20 mil wide # Clearance to polygons: gap = 12 mil ( = 24mil/2) # Gap to solder mask: 3 mil = (26mil-20mil)/2 ) It's a cumbersome and annoying, but you just have to get used to it. The problem is that we usually want to specify footprint specs in different terms than pcb requires them, like we want to say "gap from copper to solder mask" or "gap between pad and polygon". It would be so nice to have cleanly described footprints, rather than relying on layers of footprint generator scripts and stuff, or tedious manual calculations. Regards, Colin