X-Authentication-Warning: delorie.com: mail set sender to geda-user-bounces using -f X-Recipient: geda-user AT delorie DOT com X-Authority-Analysis: v=2.0 cv=bcnpoZzB c=1 sm=0 a=6jktZp3dcHAl1vye2O6wCg==:17 a=jl9P3j1e7_0A:10 a=M_ffKnrP7SkA:10 a=6WB07kdHjWAA:10 a=IkcTkHD0fZMA:10 a=VxQc-PSaXx1op5bd78QA:9 a=QEXdDO2ut3YA:10 a=wGW2LHjTb6WUgfYn:21 a=ONXXWqgDAXUurdqB:21 a=6jktZp3dcHAl1vye2O6wCg==:117 X-Cloudmark-Score: 0 X-Originating-IP: 70.113.67.117 Message-ID: <4F9C8376.2070907@ecosensory.com> Date: Sat, 28 Apr 2012 18:55:34 -0500 From: John Griessen User-Agent: Mozilla/5.0 (X11; Linux i686; rv:8.0) Gecko/20120216 Icedove/8.0 MIME-Version: 1.0 To: geda-user AT delorie DOT com Subject: Re: [geda-user] board fab References: <4F915B7C DOT 9000009 AT schinagl DOT nl> <4F959E1F DOT 6010803 AT schinagl DOT nl> <4F997E2E DOT 7010306 AT schinagl DOT nl> <4F99CEFD DOT 10707 AT schinagl DOT nl> <20120426170536 DOT 73e21755 AT svelte> <4F9A6010 DOT 7010305 AT schinagl DOT nl> <20120427064154 DOT 44e9eb77 AT svelte> <4F9AB232 DOT 9030508 AT ecosensory DOT com> <4F9C351A DOT 6000607 AT ecosensory DOT com> In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Reply-To: geda-user AT delorie DOT com On 04/28/2012 01:41 PM, Russell Dill wrote: > They are nice because you don't have to file them off, but > panelization services can't use them since the require a set back. I wonder what the dorkbotpdx guy would do if I asked him, "What's the aspect ratio of the area left to fill on the current run of medium production? If you tell me, I can generate a RS-274X blob that size that hangs together as a panel, and what price would you sell it to me for? Maybe he'd go less than $1/inch for that. PCB is a good panelizer. seeed has so many restrictions on their $0.26/inch 2 layers that I can't see using them for product. Oh, there are some customers that would not care about rough edges... The part about break-off forces means all the perimeter has to be designed with a keep away distance to avoid stress to soldered components and that's a waste also...which is another reason to skip using any randomly placed break-off tabs. Teeny boards are a good value and they are best fabbed/assembled in groups, so I'd only design my own routed edges with tabs. That series of articles by Hausherr is good. I heard him talk at a board layout tool-sales/fab-sales meeting last year and he's pretty good at describing the state of things with a US perspective. I wonder if that is even close to the Asian perspective though. Mostly he was harping on metric metric and PCB's there as of a year ago, so the only thing to do to get up with the mainstream is to learn some way to auto-generate IPC "compatible", yet not copied directly, land patterns in thin, normal, and fat proportions, since the state of the industry is to "wing it" at fab time according to the fab's needs, and shrink or bloat things to match capabilities. John