X-Authentication-Warning: delorie.com: mail set sender to geda-user-bounces using -f X-Recipient: geda-user AT delorie DOT com Date: Mon, 12 Mar 2012 17:52:59 -0400 (EDT) From: GENE GLICK Subject: Re: [geda-user] Very confused...possible PCB bug? Need help. X-Originating-IP: [12.139.224.82] To: geda-user AT delorie DOT com Cc: geda-user AT delorie DOT com Message-id: <2c336f.a312.13608e669b8.Webtop.18@optonline.net> MIME-version: 1.0 Content-type: multipart/alternative; boundary="Boundary_(ID_CB4VQ/ADhluBcPuuz2tjnQ)" X-SID: 18 X-Authuserid: geneglick AT optonline DOT net User-Agent: Laszlo Mail 3 Reply-To: geda-user AT delorie DOT com --Boundary_(ID_CB4VQ/ADhluBcPuuz2tjnQ) Content-type: text/plain; charset=UTF-8; format=flowed Content-transfer-encoding: 7BIT Content-disposition: inline On Mon, Mar 12, 2012 at 3:15 PM, DJ Delorie wrote: >> Someone mentioned "the zero-length trace problem" in private >> email; what's up with that? I haven't googled it yet but I will in >> a moment. > > If you have a trace that's so small as to be completely hidden under a > pin or pad, with the "join" flag set, then if that trace will > "connect" to a polygon even if the clearance around the pin/pad means > it really doesn't. > > I.e. DRC doesn't consider pin clearance when checking to see if a > trace connects to a polygon. Yeah - you jogged my memory . I had a problem once with a shorted trace - if I recall, it was a thermal that I added on layer-1, by accident. The polygon attached to it when I didn't mean to. Anyway, divide and conquer zeroed me in on the problem. I may have looked at the .pcb file at that point for a hint if it wasn't obvious on the gui. Anyway - divide and conquer on a backed up version only :) --Boundary_(ID_CB4VQ/ADhluBcPuuz2tjnQ) Content-type: text/html; charset=UTF-8 Content-transfer-encoding: quoted-printable Content-disposition: inline


On Mon, Mar 12, 2012 at 3:15 PM, DJ Delorie wrote:

> >&nb= sp;   Someone mentioned "the zero-length trace problem"= in private
> > email; wha= t's up with that?  I haven't googled it yet but I will in
=
> > a moment.
>
> = If you have a trace that's so small as to be completely hidden under a
> pin or pad, with the "join= " flag set, then if that trace will
> "connect" to a polygon even if the clearance around= the pin/pad means
> it reall= y doesn't.
>
> I.e. DRC doesn't consider pin clearance wh= en checking to see if a
> tra= ce connects to a polygon.

Yeah - you jogged my memory .  I had a problem once wi= th a shorted trace - if I recall, it was a thermal that I added
on layer-1, by accident. The polygon attach= ed to it when I didn't mean to. Anyway, divide and conquer zeroed me in
on the problem. I may have looked a= t the .pcb file at that  point for a hint if it wasn't obvious on the = gui.

Anywa= y - divide and conquer on a backed up version only :)
= --Boundary_(ID_CB4VQ/ADhluBcPuuz2tjnQ)--