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Date: Mon, 20 Feb 2012 16:53:31 -0800
From: Colin D Bennett <colin AT gibibit DOT com>
To: geda-user AT delorie DOT com
Subject: Re: [geda-user] verilog question - blocking/non-blocking
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On Tue, 21 Feb 2012 01:27:31 +0100
Kai-Martin <kmk AT familieknaak DOT de> wrote:

> Don't know about verilog. But VHDL compilers complain and refuse
> to synthesize such constructs inside a block. A block is the VHDL
> way to say that things should be done in parallel. Inside a
> process the snippet would be fine, since commands are executed
> sequentially.

I have only written Verilog, not VHDL, but in my experience Verilog
lets you shoot yourself in the foot too easily. It seems that VHDL
is more rigorous and robust in a number of situations, at the cost
of some added source code verbosity.  Would that be a fair
statement?

A worthwhile trade in favor of VHDL, it seems to me.

Regards,
Colin