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Date: Sun, 19 Feb 2012 23:05:46 -0700
Message-ID: <CAN0Jx--75G6GW0uqA13AEpeM9Dbw4QxrRmtzFMGUOTmXtoYsww@mail.gmail.com>
Subject: Re: [geda-user] verilog question - blocking/non-blocking
From: Russell Dill <Russ DOT Dill AT asu DOT edu>
To: geda-user AT delorie DOT com
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> I suppose the "=" (blocking) makes the code sequential, like C - if that
> clarifies it some. But I was really wondering how the synthesis tools deal
> with this. I almost always avoid using the "=" form.  It doesn't bother me
> that my states are off (delayed) by 1 clock tick.  So in my 2nd example,
> during simulation do_something runs when the counter is 1 not 0. Not really
> a big deal. In the first example, do_something runs when the counter is 0.
> Makes looking at the waveforms, and the counter, line up nice but what the
> heck does the synthesis tool build?

Xilinx has a series of great videos on how to make verilog that their
tool likes. It generally offers a pretty good explaination of why
things should be done a certain way and the information is probably
useful across other synthesis tools.