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Date: Mon, 20 Feb 2012 00:42:48 -0500
From: gene glick <geneglick AT optonline DOT net>
Subject: Re: [geda-user] verilog question - blocking/non-blocking
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On 02/20/2012 12:17 AM, DJ Delorie wrote:

> always @(posedge clk)
>    begin
>       /* edge happens here */
>       new_count = count + 1;
>       if (new_count == 0)
>         do_something
>       count = new_count;
>    end
>
>
> always @(posedge clk)
>    begin
>       prev_count = count;
>       /* edge happens here */
>       count<= prev_count + 1;   // non-blocking method
>       if (prev_count == 0)
>         do_something
>    end
>
>
> My personal paradigm is to use '=' in an @always combinatoric state
> machine that computes the next state from the current state, and '<='
> in a separate edge-triggered @always that just copies the next state
> to the current state.
>
> For example, see http://www.delorie.com/electronics/sdram/simple1.v
>
> The last two blocks are an "always @(negedge ram_wclock) begin" that
> copies the next state to the current state, followed by a huge "always
> @(...lots of things...)" that computes the next state.
>
> I've found that if I try to mix combinatoric and edge logic in the
> same block, I end up doing something pessimal and the chip won't run
> as fast as it should.
>

I suppose the "=" (blocking) makes the code sequential, like C - if that 
clarifies it some. But I was really wondering how the synthesis tools 
deal with this. I almost always avoid using the "=" form.  It doesn't 
bother me that my states are off (delayed) by 1 clock tick.  So in my 
2nd example, during simulation do_something runs when the counter is 1 
not 0. Not really a big deal. In the first example, do_something runs 
when the counter is 0. Makes looking at the waveforms, and the counter, 
line up nice but what the heck does the synthesis tool build?

Wouldn't your method of 'previous count' and 'count' use twice as many 
registers?