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Date: Sun, 19 Feb 2012 20:38:44 -0800
From: Traylor Roger  <traylor AT eecs DOT oregonstate DOT edu>
To: geda-user AT delorie DOT com
Subject: Re: [geda-user] verilog question - blocking/non-blocking
Message-ID: <20120220043844.GA26101@slana.eecs.oregonstate.edu>
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Gene,
  A good place to find info on this is:
  http://www.sunburst-design.com

  Especially see the paper: 
  Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill!

Roger

On Sun, Feb 19, 2012 at 11:24:42PM -0500, gene glick wrote:
> consider this code:
> 
> always @(posedge clk)
>  begin
>     count = count + 1;    // blocking method
>     if (count == 0)
>       do_something
>  end
> 
> 
> then this way . . .
> 
> 
> always @(posedge clk)
>  begin
>     count <= count + 1;   // non-blocking method
>     if (count == 0)
>       do_something
>  end
> -------------------------------------------
> 
> The 1st way, do_something occurs when the count is actually at 0. The 
> second way, do_something occurs when the count is 1. Subtle difference. 
> I don't have a synthesis tool ready to run, otherwise I'd try it. 
> Question : does one method synthesize significantly different logic than 
> the other?
> 
> 
> 
>