Sorry for the late response. I had = a death in the family and have fallen behind in correspondence.

On Apr 19, 2021, at 8:23 AM, Chad Parker (parker DOT charles AT gmail DOT com) [via geda-help AT delorie DOT com] <geda-help AT delorie DOT com> wrote:

Hi Roger-

Sorry for the = frustration.

It happens=E2=80=A6its all in how we deal with it. = Life, software, most other things...;^)

I believe that DRC warning is somewhat recently added. One of = the flags that can be set on many objects is called the "clearline" = flag. This flag is used to indicate that a particular object (line, arc, = via) should create a clearance around itself inside of polygons. If this = flag is NOT set, then that clearance is not created, and the object is = electrically connected to the polygon.

The assumption is that if the clearline = flag is NOT set, that the user wants that particular object to be = connected to a polygon. So, DRC checks to see if that's the case, and if = an object does not have the clearline flag set and is not touching a = polygon, it raises a warning. So, in your case, I would suggest looking = at the objects in question and checking these flags. If you have any = objects that are not connected to polygons that also do not have the = clearline flag set, you can set the clearline flag and that should make = the warning go away.

If you've reviewed the area and are confident that the design = meets your requirements, then you can probably ignore those errors. = Their primary purpose is to make sure that pcb did what you intended.

I've= worked pretty hard to make sure the DRC works as advertised, but it's = always possible that there's a bug. The whole system is based on a = suboptimal framework that I've been upgrading slowly. If you believe = you've found a bug, it would be very helpful if you could file a bug = report or send me a pcb file that demonstrates the behavior that you = believe is an error.

Thank you for the insight into what may have been = going on. I believe you are the right path to the problem I was having. = My solution

was brute force however not seeing anything = amiss with either the polygons or lines that were intended to be = connected to them. I

still have no idea on what = caused the error to appear. I am suspicious of the vias = though.

My solution was to remove = polygons and see what DRC did afterwards. When I was finally down to one = polygon and a few errors, I began

to remove lines and vias to = see what the effect would be. Lines that were to be connected to poly = were. Vias seemed to be connecting

from top to bottom = polygons where I would expect. However when I removed the last via from = top to bottom copper the last DRC error

disappeared. I put = back the via and the line to it and no errors cropped up. I then = redid all the poly areas, vias and lines checking at each

edit = for DRC errors. None occurred. It seemed like I must have done something = to change a clear line flag somewhere, maybe on a

via, by = accident.

I=E2=80=99ve never = seen this error before so I am assuming cockpit error or clumsy fingers. = Right now I have a clean DRC and am preparing

to send for = fabrication. Thank you for your work on the DRC and on making PCB a = usable tool. I truly appreciate your efforts.

Take care and thanks again for your = response,

Roger = Traylor

Thanks,
--Chad

On Sun, Apr = 18, 2021 at 3:38 AM Roger Traylor (traylor AT engr DOT orst DOT edu) [via geda-help AT delorie DOT com] <geda-help AT delorie DOT com> wrote:
Folks,

Was putting final touches on a design and after some edits now I get
multiple "joined line/via not connected to polygon" errors. I had been =
increasing the line width of a few traces and little else.
=
I quit the tool hoping for some resolution as I had seen some errors = related
to incorrect serial numbers on undo=E2=80=99s. I saved and restarted as = the tool advised
so undoing to get back to square one is not an option.

I have looked at most of the errors flagged. They are all in an area = where
both top and bottom layers (2.4Ghz, 2 layers) can be used as ground = planes.
Many of the traces have never had a connection to either plane and = furthermore
I did not touch them in the final edit session. Others have always been =
connected to the ground plane via a join(on top) followed by a via to = both sides
using thermal tool to connect to both planes.

I think DRC is lying to me. Have looked for hours but cannot find what = is
going on. The only difference in the pieces of the polygons I can find = is that
the object report for most is =E2=80=9Cclearly, selected,fullpoly=E2=80=9D= while one other piece
includes =E2=80=9Cfound=E2=80=9D. Can someone throw me a idea?

Running PCB 4.2.2 on Ubuntu 19.10.

Thanks in advance,
Roger Traylor