X-Authentication-Warning: delorie.com: mail set sender to geda-help-bounces using -f X-Recipient: geda-help AT delorie DOT com X-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:subject:message-id:in-reply-to:references:reply-to :organization:disposition-notification-to:return-receipt-to :mime-version:content-transfer-encoding; bh=KWf7r7gBl3d3vwGB9HRV3YPympzNNutIL9OrUKDR0pc=; b=BVQ06uk9/MND1XMkhN+GX+Ol4/ZNje5tTSiPxQ6+6qT2vHmzbOukoNiL1Kowk49jFQ 6g7g0dzWcIJ/STHqVP5nmu6nOmGZ8JrLRh0KOoStCMUKPfxZoQfjeQgZlCjtP4Ti9t5F tPryB0jS/lJn0fZXbBU1g7ZEIezxgX2FD55It5jgSz3Xg7qseUIw2zqT4HEkJkwN1bBG GcA01bUtBTA/z74w16qWMAHx8aniNyhBAbF7Ls7akSnO75DRd7i9GX3czA4+74iOAVc/ yWoPwNFVmg/Tt9RuxXIFCwkN/lEflGSrubiCq8OwN8MCKs6CZwbBOz1e40F4dnFqm3SE eHfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:subject:message-id:in-reply-to :references:reply-to:organization:disposition-notification-to :return-receipt-to:mime-version:content-transfer-encoding; bh=KWf7r7gBl3d3vwGB9HRV3YPympzNNutIL9OrUKDR0pc=; b=QJZkwk1B98dcEfjm3c38pGrDotjv43vv7TD8LZ2fSUcv9eRUBvCf+IFN6uiVbn91tn zn7p26C2slHP/FU06sC3WLIlNKD0ScVX9TagvE7S31hvik0CkMrEkdkifEkY2VLpCoWZ Qi/PTZbnbvuayZwjTbmVCXJHVXIlT32IfIYLOkP/Xq268d+7A6M4/5DWJ0ZVkwMovskU YlUU+BtXawj0dhwWKYi/jJg0Uk2En452O+AmFUwkRLz55NQrqpUY841paV2zF7BsFFnn 2gOXXTtrNOl4MoYy5hDG2d7wKyAsTtZwtx4edg2gRrBcd6uFaLZ7Bf0rdaf0L8hjqk4n N6DA== X-Gm-Message-State: APjAAAV3s64+LVaJxv+dHNdPE1qVVL1wE8xPK2VQ4GEkpRSyIt4ddhO3 O6GrcI9EKpTfGwgrcpna7LUw7uw= X-Google-Smtp-Source: APXvYqwLp45B5Y+uRb/CBh9fVEt/oXeuipUK/SAHe1YtmKcA1yFXGO8kCv83YbVZzLFazxqO7JTnXQ== X-Received: by 2002:a0c:fe47:: with SMTP id u7mr26157902qvs.141.1572390258502; Tue, 29 Oct 2019 16:04:18 -0700 (PDT) Date: Tue, 29 Oct 2019 23:04:05 +0000 From: "John L. Males (jlmales AT gmail DOT com) [via geda-help AT delorie DOT com]" To: geda-help AT delorie DOT com Subject: Re: [geda-help] Question: New User - Can One Create a Part with Via connected with Trace to Pad? Message-Id: <20191029230405.ac550b0ecd2669dcbdf59f0c@gmail.com> In-Reply-To: References: <20191028213830 DOT 2e35bc6023c2d8a37696bcd5 AT gmail DOT com> Organization: Toronto, Ontario X-Mailer: Sylpheed 3.7.0 (GTK+ 2.24.32; amd64-portbld-freebsd11.2) Disposition-Notification-To: jlmales AT gmail DOT com X-Compose-Start-Epoch: `date +%s` Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Reply-To: geda-help AT delorie DOT com Errors-To: nobody AT delorie DOT com X-Mailing-List: geda-help AT delorie DOT com X-Unsubscribes-To: listserv AT delorie DOT com Precedence: bulk -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello Chad, Thanks for your reply. First and key comment is I did try prior to my question to run PCB from command line to find out what PCB would indicate about the various attempts, even on own a single item, for Vias and Lines. PCB issues no error messages to the command line. Like using PCB from a GUI start PCB simply starts and stops with no message of the error in the part library. I would think PCB should issue some sort of message or messages of what PCB found unacceptable rather than starting and stopping (or crashing). I will try your excellent creative suggestions. I do not know what is involved or how much coding effort may be involved, but it would seem in my opinion that being able to use any PCB statement in a part could have real useful and powerful benefits. I also suspect having PCB be able to use any PCB statement in a part may not be sensed as something many might use because the functionality has not been part of PCB for as long as PCB has existed. This then becomes the classic did the chicken or e.g. appear first. Again, just my thoughts and opinions in regards to suggestions for PCB enhancements and not a negative of existing design of PCB. I may find if I try to input a schematic with gEDA tools (I may have many schematic and footprint parts to create to accomplish) I may in fact also find it useful for parts layout to be able to make PCB libraries to enhance the schematic to PCB design. I have not decided if I will use a gEDA program for schematic capture until I have evaluated the various factors if makes sense for me personally to do so. John L. Males Toronto, Ontario Canada 29 October 2019 19:04 -0400 EDT ================================================================ 2019-10-29 22:43:39+0000-UTC Time: 1572389019 PC/System time 29 Oct 22:43:39 ntpdate[38846]: ntpdate 4.2.8p12-a (1) 29 Oct 22:43:54 ntpdate[39143]: step time server 24.72.10.235 offset -1.140686 sec FreeBSD 11.3-STABLE FreeBSD 11.3-STABLE #0 r349903: Thu Jul 11 16:13:47 UTC 2019 root AT releng2 DOT nyi DOT freebsd DOT org:/usr/obj/usr/src/sys/GENERIC (Work in progress alternative to Linux Kernel of its own right, Debian, and other Linux based Kernel distributions determined.) Intel(R) Core(TM) i3-2367M CPU @ 1.40GHz Intel(R) Core(TM) i3-2367M CPU @ 1.40GHz (1396.86-MHz K8-class CPU) Intel(R) Core(TM) i3-2367M CPU @ 1.40GHz (1396.86-MHz K8-class CPU) Intel(R) Core(TM) i3-2367M CPU @ 1.40GHz (1396.86-MHz K8-class CPU) Intel(R) Core(TM) i3-2367M CPU @ 1.40GHz (1396.86-MHz K8-class CPU) Intel(R) Core(TM) i3-2367M CPU @ 1.40GHz (1396.86-MHz K8-class CPU) dev.cpu.0.temperature: 68.0C dev.cpu.1.temperature: 68.0C dev.cpu.2.temperature: 65.0C dev.cpu.3.temperature: 64.0C hw.acpi.thermal.tz0.temperature: 68.1C vmstat -s: 1400988395 cpu context switches 52778995 device interrupts 7627659 software interrupts 200007766 traps 3720236386 system calls 27 kernel threads created 8922 fork() calls 6450 vfork() calls 6 rfork() calls 128650 swap pager pageins 684626 swap pager pages paged in 141005 swap pager pageouts 1209794 swap pager pages paged out 34731 vnode pager pageins 277201 vnode pager pages paged in 794 vnode pager pageouts 6400 vnode pager pages paged out 1334 page daemon wakeups 328293744 pages examined by the page daemon 0 clean page reclamation shortfalls 11838475 pages reactivated by the page daemon 848055 copy-on-write faults 7836 copy-on-write optimized faults 146665618 zero fill pages zeroed 15648 zero fill pages prezeroed 132428 intransit blocking page faults 207249218 total VM faults taken 168193 page faults requiring I/O 0 pages affected by kernel thread creation 659440 pages affected by fork() 227599 pages affected by vfork() 248 pages affected by rfork() 206624561 pages freed 37863730 pages freed by daemon 55771934 pages freed by exiting processes 727486 pages active 447115 pages inactive 314621 pages in the laundry queue 418209 pages wired down 100300 pages free 4096 bytes per page 81057631 total name lookups cache hits (88% pos + 1% neg) system 0% per-directory deletions 0%, falsehits 0%, toolong 0% Boot time : 1572137847 procs memory page disks faults cpu0 cpu1 cpu2 cpu3 r b w avm fre flt re pi po fr sr ad0 pa0 in sy cs us sy id us sy id us sy id us sy id 0 0 0 38432448 401140 825 47 1 1 823 1307 0 0 210 14811 5577 12 6 83 13 4 83 13 4 84 13 4 84 memory info: real memory = 8589934592 (8192 MB) avail memory = 8166465536 (7788 MB) last pid: 41398; load averages: 0.65, 0.69, 0.84 up 2+21:46:28 22:43:55 72 processes: 2 running, 70 sleeping Mem: 2842M Active, 1747M Inact, 1229M Laundry, 1634M Wired, 773M Buf, 391M Free Swap: 48G Total, 2134M Used, 46G Free, 4% Inuse hw.physmem: 8463925248 hw.usermem: 6750781440 hw.realmem: 8589934592 total used free shared buffers cached Mem: 8030732 5839660 2191072 0 0 0 Swap: 50331644 2185192 48146452 swapinfo: Device 1K-blocks Used Avail Capacity /dev/ada0s1b 50331644 2185192 48146452 4% vmstat: procs memory page disks faults cpu r b w avm fre flt re pi po fr sr ad0 pa0 in sy cs us sy id 2 0 0 38432416 401116 825 47 1 1 823 1307 0 0 210 14811 5577 12 4 83 Message replied to: Date: Tue, 29 Oct 2019 13:24:31 -0400 From: "Chad Parker (parker DOT charles AT gmail DOT com) [via geda-help AT delorie DOT com]" To: geda-help AT delorie DOT com Subject: Re: [geda-help] Question: New User - Can One Create a Part with Via connected with Trace to Pad? > pcb "elements" (footprints) support only a small subset of > pcb features, including pins, pads, and silk lines/arcs. > Anything you want in a element has to be one of these things. > > You can create the via in your element as a pin. pcb treats > pins and vias identically in nearly all circumstances. You > can create the trace in your element, and call it a pad. In > fact, when you're creating footprints with the GUI, you draw > the pads as lines, and then convert the lines to pads at the > end of the process. So, if you want to draw a line in a > footprint, you can, you just have to convert it to a pad. > This does limit you in that you can only put pads on the > outer layers of pcbs. > > The presence or absence of components should be essentially > irrelevant. pcb doesn't care one way or the other. > > --Chad > > On Mon, Oct 28, 2019, 18:04 John L. Males (jlmales AT gmail DOT com) > [via geda-help AT delorie DOT com] wrote: > > > -----BEGIN PGP SIGNED MESSAGE----- > > Hash: SHA1 > > > > Hello, > > > > I have a part with a pair of square solder pads that is > > like an oversized SMD pad. > > > > I have been trying a number of different ways to add to the > > part a Via that has a connecting trace between the Via and > > one of the two square pads as a part. I have looked ad > > different parts to see if I can figure out how to > > accomplish this as well as searching the internet. After a > > few days of trying I am stumped. > > > > The reason for such a part is to enable it to be easy > > to create PCB variations not only with ease and quickly, but > > accurately. This PCB has no components which I suspect is > > why what I am trying to accomplish is a challenge. I have > > a part for the air flow holes and a part for the screw > > mounting holes. > > > > First question is creating a part with a Via, and connecting > > trace to a pad is possible? > > > > Second question is would I be safe to assume if the first > > question is possible it means I could create a trace > > connecting a copper area to a pad that doe not need a Via? > > > > The first question is so I can connect the bottom copper > > area to top side of PCB to avoid the trace being on bottom > > side of PCB that will be mounted to metal support. There > > is enough space between the edge of copper area and the > > metal support to place a via at the edge of the copper area > > to enable the connecting trace to be on the top side of PCB > > so the trace makes no contact with metal. > > > > > > John L. Males > > Toronto, Ontario > > Canada > > 28 October 2019 17:38 -0400 EDT > > > > > > > > -----BEGIN PGP SIGNATURE----- iF0EARECAB0WIQQxRId2q5JPHFiozTr5X9dS0HpoEAUCXbjFZQAKCRD5X9dS0Hpo EJEiAJ9JfdeKiexHPwZZp0wDHU6mKQWH1QCgpslzpNUs8mIhV+MO33KnKptLEJw= =qyQr -----END PGP SIGNATURE-----