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<11BDEC14-5D1D-4157-B552-582C1E75D00E AT noqsi DOT com> <20170218180232 DOT GB23464 AT localhost DOT localdomain> <4FA4C5C8-4B56-493A-94AC-1D4920C201F3 AT noqsi DOT com> <20170218185614 DOT GA25608 AT localhost DOT localdomain> <20170218202533 DOT GA6290 AT localhost DOT localdomain> <4E40A607-349A-440A-8EB2-8DD478E510B5 AT noqsi DOT com> From: "Peter Clifton (petercjclifton AT googlemail DOT com) [via geda-help AT delorie DOT com]" Date: Sun, 19 Feb 2017 08:27:15 +0000 Message-ID: Subject: Re: [geda-help] Please help with multiple-pages schematics To: geda-help AT delorie DOT com Content-Type: multipart/alternative; boundary=94eb2c04f19a2046f40548ddea5e Reply-To: geda-help AT delorie DOT com Errors-To: nobody AT delorie DOT com X-Mailing-List: geda-help AT delorie DOT com X-Unsubscribes-To: listserv AT delorie DOT com Precedence: bulk --94eb2c04f19a2046f40548ddea5e Content-Type: text/plain; charset=UTF-8 On 19 Feb 2017 04:47, "Vasily Olekhov (olekhov AT gmail DOT com) [via geda-help AT delorie DOT com]" wrote: Thank you everyone. Yes, naming nets that span across the pages helps. Yet, naming by hand most of QFP144 pins is quite labour-intensive. Do you need these all to be off page? Having good netnames is often useful in general, but isn't required if you can wire up what you need with nets on a particular page. Whilst as others have pointed out, you can't really use CONN1 on multiple pages (with the same pins), you certainly CAN split the symbol for a large component into multiple pieces (all with different pins), and use them in different places / pages. This is typically how FPGAs get done, or large system on chip devices where there are so many pins it is impractical to use a single symbol. You might have one symbol for the pins on each IO bank, for example. Another for power. Another for JTAG etc.. At the smaller level, we often do something similar for multiple opamps or gates in a package. There is a mechanism called "slotting" which lets you define symbols that change pin number depending upon which device (slot) number in the chip you are adding to the schematic. (This is something to look at later perhaps, once you are happy with the basic parts of the tools). Peter C --94eb2c04f19a2046f40548ddea5e Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable

On 19 Feb 2017 04:47, "Vasily Olekhov (olekhov AT gmail DOT com) [via geda-help AT delorie DOT com]" <geda-help AT delorie DOT com> wrote:
<= blockquote class=3D"quote" style=3D"margin:0 0 0 .8ex;border-left:1px #ccc = solid;padding-left:1ex">

Thank you everyone.

Yes, namin= g nets that span across the pages helps.

Yet, nami= ng by hand most of QFP144 pins is quite labour-intensive.

Do y= ou need these all to be off page?

Having good netnames is often useful in general, but isn't re= quired if you can wire up what you need with nets on a particular page.

Whilst as others have point= ed out, you can't really use CONN1 on multiple pages (with the same pin= s), you certainly CAN split the symbol for a large component into multiple = pieces (all with different pins), and use them in different places / pages.=

This is typically how F= PGAs get done, or large system on chip devices where there are so many pins= it is impractical to use a single symbol.

You might have one symbol for the pins on each IO bank, = for example. Another for power. Another for JTAG etc..

At the smaller level, we often do something = similar for multiple opamps or gates in a package. There is a mechanism cal= led "slotting" which lets you define symbols that change pin numb= er depending upon which device (slot) number in the chip you are adding to = the schematic. =C2=A0(This is something to look at later perhaps, once you = are happy with the basic parts of the tools).

Peter C

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