X-Authentication-Warning: delorie.com: mail set sender to geda-help-bounces using -f X-Recipient: geda-help AT delorie DOT com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=yahoo.com; s=s2048; t=1412786933; bh=e4qEKvjHL6DgfcgSHxqw7F9syQ21SKzjvOiP9nmXy7Q=; h=Date:From:Reply-To:To:In-Reply-To:References:Subject:From:Subject; b=BfJz5L7VhZ9KShGxJkMsSXr1Al4y1SjQn7KxhsogD1K2oMOk2pvhIaclRe0MjMfynFZPUV6jgzm4c49JyW+UHD8BGRbebOCrWi5N6QNVfNEFgrFF5YoLjmg/R8z/yj/e0tacgAxvY2/0ydSvIvAMcbeVKmwrteWtk9cgplTNYU++toMfYG5xIzbjqSddgzgVsb7Y0YUh+EBL3vv/NpVs9PivrkaUeqiNs1c2G/4NlRqP+0eOgY65YJt5Jg0N2ESgxXD7jJu1YZVg7L5LOT4IrwifCFAtjRZSIwA4kO+Dr2xAssuVl0L7Wj3HWF59HbuM9CwjW5HKSZqwar52bq5Cww== DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=s2048; d=yahoo.com; b=JytIEx1Tc5kG4TBpdi3aMKyk7tWosGvw0jsUMoJ6TNu248NmqCt7caRQcTpCiA8DeS4Ebie/Cmwodux+NTYC3DEauhFeuSydQarauTzLNFX3yURyEGeaYuoaA61QJzcif+feyO5l9VTBXflK3qdEEQ6KYQwSJJZLtHE/AdEhdtUBbzgTfsex8gPeGwyq6wzqo5prTDUFqFBkUQxRhAuEb+Tro21d/DG/a8MRaNdT2NeO2NmAFVBKHfYH3ID+tyUFYcTMtLro9SU7SKpXXqJ+0pkGRbMmLJfW2KSyzLvwwjFvW1y61zTkdrIvDnPE73lHfR6vLlmtZ3e8JIkvU5WZzg==; X-Yahoo-Newman-Property: ymail-3 X-Yahoo-Newman-Id: 779724 DOT 93771 DOT bm AT omp1059 DOT mail DOT bf1 DOT yahoo DOT com X-YMail-OSG: KkOh2HIVM1mdmLdCYslZLVtbGYdx5Bt70Yz.EJiRD0ndUqgum_kUdMp0GnXfZXq p9.__a6IfdOrVafYb52fd8FXJgF0rf4._fbaFlybAfk.QPllmNEjP1CtSCcT6.FIVeTIoDeXczLh Nc9qluASntrHLQPRyydAKXBIJFT2Wk3Cu_041.DEy30W5rp.M1WNXEhRv_ZRvwIuszgzoBWoii8F 6kj75N6zOtwM03oTWWE90mwUivIPE1AqMy5UX_HinuPUPZPm3WcgqsUwTgiDJojaHYZ5olZKDMju EgO9wrJL2Ithzo.sJspT7foed.UUCQiSyoeUsps57thmrTvEJlZxbJrCI4RwjzLn8E9h_WmMdZaz Hl.7jbnMC_lkRBU8FcDckhmdGqqXeI1RQET3A4QfAdLtC4pY2NS6aHwo.EPvuUNglHXjUT_.L5Dv z18HbaNzn7utXroUY6u55T6H2fDwJ7b5JuNWEmI36LCDcw6IDORPQ3EWylL7ArVJ8R5SIyNmLkys- Date: Wed, 8 Oct 2014 16:48:51 +0000 (UTC) From: Jason McLafferty To: "geda-help AT delorie DOT com" Message-ID: <685015500.1106923.1412786931337.JavaMail.yahoo@jws10651.mail.bf1.yahoo.com> In-Reply-To: <1412784061.2815.98.camel@linetec> References: <1412784061 DOT 2815 DOT 98 DOT camel AT linetec> Subject: Re: [geda-help] Panelizing howto or examples? MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="----=_Part_1106922_2126294198.1412786931328" Reply-To: geda-help AT delorie DOT com Errors-To: nobody AT delorie DOT com X-Mailing-List: geda-help AT delorie DOT com X-Unsubscribes-To: listserv AT delorie DOT com Precedence: bulk ------=_Part_1106922_2126294198.1412786931328 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Hi Richard, I have panelized boards that I later separate myself.=C2=A0 To do this, I d= raw a line on the top silk layer so I know where I want to cut the boards. Here is the approach I have used to do this in pcb:(1) Make sure settings -= > "Require Unique Element Names" is NOT selected.=C2=A0 This makes sure eac= h copy of the board on the panel has the same part number for each part.=C2= =A0 Otherwise, for example, R1 on the original board becomes R(some other n= umber) on the next copy on the panel.(2) Figure out what size the overall p= anelized board is going to be, being sure to allow for kerf for separating = the boards plus any extra you want. (3) Resize the board according to what you come up with in step (2) (File -= > Preferences, sizes on left side).(4) To align boards for pasting the layo= ut, I draw lines:(a) I draw lines on the OUTLINE layer to start (you'll see= why...)=C2=A0 I place these lines where I want the edge of the copies of t= he original board to end up as I panelize.(c) Say I want to lay out the pan= el as a row of boards.=C2=A0 I drop the measurement origin (CTRL + m) on th= e top right corner of my original board.=C2=A0 The I use the coordinates to= go the proper horizontal distance (the kerf plus any extra spacing).=C2=A0= This is left edge of next board on panel.(d) Now I draw a vertical line on= the OUTLINE layer.(e) Next, de-select the OUTLINE layer (so it is invisibl= e).(5) Mouse over the center of the original board.(6) ALT-a selects all la= yers of the original board.(7) CTRL - C copies all layers to a buffer.(8) N= ow, turn back on OUTLINE layer.=C2=A0 The line indicating the left edge of = the new board re-appears.(9) Click on the copied layers (original board - I= think it changes to light blue when it has been copied to buffer IIRC).(10= ) Drag the copy to the right until the left edge of the copied board is cen= tered on the OUTLINE layer that you drew to indicate the placement of the l= eft edge of board.(11) Repeat steps until you have all copies of board plac= ed on panelized board.(12) Now, convert the OUTLINE board edges to SILK lin= es.=C2=A0 The board house I use only wants one outline, for the entire boar= d.=C2=A0 By using SILK lines, they will show up and I know where to cut.(a)= Trace the OUTLINE board edges in SILK lines.(b) Turn off SILK layer so the= original OUTLINE lines are visible.(c) Delete these OUTLINE lines so the b= oard manufacturer is not confused where the outline layer is.(d) Now make s= ure the panelized board has its outline draw on the OUTLINE layer. That should be all the steps.=C2=A0 Of course, I usually save a lot of inte= rmediate files during the process in case I make a mistake and need to reve= rt. Hope this helps! Jason =20 On Wednesday, October 8, 2014 12:01 PM, Richard Rasker wrote: =20 Hello, I've got a small PCB (38 mm x 21.4 mm, 12 components) that I'm trying to panelize. The idea is to use a a routed outline that is connected to the panel by its two right-hand corners -- see attached PCB file for an example. I simply created breaks in the outline, copied the single PCB, and drew a new outline around the panel (the actual panel will be somewhat larger, of course -- this is my first attempt at panelizing). However, when I upload the exported Gerber files to my usual PCB manufacturer (Eurocircuits) and have it analyzed, I get an error about an unrecognized file format. I think that their analysis tools are confused by non-closed and nested outlines. I also found a reference to DJ Delorie's panelize plug-ins for PCB, but I have no clue how to actually 'plug these in' in PCB -- I have Mehanik's repository active, but the pcb-plugins package is not found.=20 Also, I assume that it should be a simple matter of copying PCB's and perhaps juggle outlines and/or add some layer or other. Or is panelizing something not done within PCB? Of course I can simply tell the manufacturer to panelize these for me, but then the cutting points can end up anywhere, which makes for a lot of fiddly machining afterwards. Is there a simple explanation somewhere, and/or perhaps some example files? Thank you in advance, Best regards, Richard Rasker ------=_Part_1106922_2126294198.1412786931328 Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable
Hi Richard,
=

I have panelized boards that I later sep= arate myself.  To do this, I draw a line on the top silk layer so I kn= ow where I want to cut the boards.

Here is the approach I have used to do this in pcb:
(1) Make sure settings -&= gt; "Require Unique Element Names" is NOT selected.  This makes sure e= ach copy of the board on the panel has the same part number for each part.&= nbsp; Otherwise, for example, R1 on the original board becomes R(some other= number) on the next copy on the panel.
(2) Figure out what size the overall panelized bo= ard is going to be, being sure to allow for kerf for separating the boards = plus any extra you want.
(3) Resize the board according to what you come up with in s= tep (2) (File -> Preferences, sizes on left side).
(4) To align boards for pasting the= layout, I draw lines:
(a) I draw lines on the OUTLINE layer to start (you'll see why...)=   I place these lines where I want the edge of the copies of the origi= nal board to end up as I panelize.
(c) Say I want to lay out the panel as a row of boards= .  I drop the measurement origin (CTRL + m) on the top right corner of= my original board.  The I use the coordinates to go the proper horizo= ntal distance (the kerf plus any extra spacing).  This is left edge of= next board on panel.
(d) Now I draw a vertical line on the OUTLINE layer.
(e) Next, de-select the OU= TLINE layer (so it is invisible).
(5) Mouse over the center of the original board.
<= div id=3D"yui_3_16_0_1_1412785754232_4832" dir=3D"ltr">(6) ALT-a selects al= l layers of the original board.
(7) CTRL - C copies all layers to a buffer.
(8) Now, turn back on OUTL= INE layer.  The line indicating the left edge of the new board re-appe= ars.
(9) Click= on the copied layers (original board - I think it changes to light blue wh= en it has been copied to buffer IIRC).
(10) Drag the copy to the right until the left edg= e of the copied board is centered on the OUTLINE layer that you drew to ind= icate the placement of the left edge of board.
(11) Repeat steps until you have all copie= s of board placed on panelized board.
(12) Now, convert the OUTLINE board edges to SILK l= ines.  The board house I use only wants one outline, for the entire bo= ard.  By using SILK lines, they will show up and I know where to cut.<= /div>
(a) Trace the = OUTLINE board edges in SILK lines.
(b) Turn off SILK layer so the original OUTLINE lines = are visible.
(= c) Delete these OUTLINE lines so the board manufacturer is not confused whe= re the outline layer is.
(d) Now make sure the panelized board has its outline draw on th= e OUTLINE layer.

That should be all the steps.  Of course= , I usually save a lot of intermediate files during the process in case I m= ake a mistake and need to revert.

Hope this helps!

Jason


On Wednesday, October 8, 2014 12:01 PM, Richard = Rasker <rasker AT linetec DOT nl> wrote:


Hello,

I've got a small PCB (38 mm x 21.4 m= m, 12 components) that I'm trying to
panelize. The idea is to use a a ro= uted outline that is connected to the
panel by its two right-hand corner= s -- see attached PCB file for an
example.

I simply created break= s in the outline, copied the single PCB, and drew
a new outline around t= he panel (the actual panel will be somewhat
larger, of course -- this is= my first attempt at panelizing).

However, when I upload the exporte= d Gerber files to my usual PCB
manufacturer (Eurocircuits) and have it a= nalyzed, I get an error about
an unrecognized file format. I think that = their analysis tools are
confused by non-closed and nested outlines.
=
I also found a reference to DJ Delorie's panelize plug-ins for PCB, but=
I have no clue how to actually 'plug these in' in PCB -- I have
Meha= nik's repository active, but the pcb-plugins package is not found.
Also= , I assume that it should be a simple matter of copying PCB's and
perhap= s juggle outlines and/or add some layer or other.
Or is panelizing somet= hing not done within PCB?

Of course I can simply tell the manufactur= er to panelize these for me,
but then the cutting points can end up anyw= here, which makes for a lot
of fiddly machining afterwards.

Is th= ere a simple explanation somewhere, and/or perhaps some example
files?
Thank you in advance,

Best regards,

Richard Rasker
<= br>
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