X-Authentication-Warning: delorie.com: mail set sender to djgpp-bounces using -f
From: philippe <philippe DOT meynard AT vendeeconcept DOT com>
Newsgroups: comp.os.msdos.djgpp
Subject: Re: jitter between 2 hardware interrupt
Date: Mon, 8 Mar 2010 01:33:44 -0800 (PST)
Organization: http://groups.google.com
Lines: 55
Message-ID: <d33c0554-f8eb-4af4-a7b0-024b8cb4e8fa@33g2000yqj.googlegroups.com>
References: <201003041907 DOT o24J7K5f029877 AT delorie DOT com> <607b5402-a0d4-4151-bf50-9ff3dbf0cd4b AT i25g2000yqm DOT googlegroups DOT com>
NNTP-Posting-Host: 80.70.37.40
Mime-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: quoted-printable
X-Trace: posting.google.com 1268040824 16902 127.0.0.1 (8 Mar 2010 09:33:44 GMT)
X-Complaints-To: groups-abuse AT google DOT com
NNTP-Posting-Date: Mon, 8 Mar 2010 09:33:44 +0000 (UTC)
Complaints-To: groups-abuse AT google DOT com
Injection-Info: 33g2000yqj.googlegroups.com; posting-host=80.70.37.40; 
	posting-account=YIu_DQoAAABQWWAQMU9nbFpLINHek5WR
User-Agent: G2/1.0
X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 
	2.0.50727; InfoPath.1; .NET CLR 1.1.4322),gzip(gfe),gzip(gfe)
Bytes: 3398
To: djgpp AT delorie DOT com
DJ-Gateway: from newsgroup comp.os.msdos.djgpp
Reply-To: djgpp AT delorie DOT com

On Mar 6, 4:13=C2=A0pm, RayeR <gl DOT  DOT  DOT  AT centrum DOT cz> wrote:
> I suspect that this behavior have something to do with PC SMBIOS/SMI.
> This is heavily used in modern PC for power management, error
> signalling and even emulating legacy hardware.
>
> CPU can be set in real mode, protected mode and SMM (System Management
> Mode) mode.
> SMM mode is entered when SMI (System Management Interrupt) is
> triggered.
> CPU has separated SMI pin that is fed from chipset. It has higher
> priority than NMI and I think it
> cannot be disabled for safety reasons. When SMI occured CPU switch to
> SMI handler.
> This is done in real mode as well as in protected mode. Entire CPU
> context is saved.
> SMI handler determine the cause of SMI and call the matching service.
> It can take some time of course.
> Finally it restore CPU context and switch back to RM/PM. So running
> operating system cannot recognize
> this interrupt. I think this approach is also used for USB storages
> emulating real drives. SMI
> BIOS cannot be completly disabled but by disabling some legacy support
> or power management stuff
> you may save some time... If you run your program on some old 486 or
> Pentium 1 you should
> notice much less jitter caused by this.
>

it's possible to disable it ?

> Next I give you warning when using RDTSC. On mobile systems there are
> various power saving features
> like intel speedstep or EIST that cause CPU clock mudulation or
> dynamic core multiplier change which
> cause that you cannot rely on TSC that it runs on constant speed! I
> had some bad story with this when
> trying to use TSC for some short time measurement.
>

yes, but I test on 2 or 3 minutes and I have the jitter. I don't think
that CPU clock change during this testing. But for a long test, I
should be careful!


> On 4 b=C5=99e, 20:07, "Josep M." <josepma DOT  DOT  DOT  AT turomas DOT com> wrote:
>
>
>
> > I don't know why, but there are som bios task wich interrupts processor=
 and
> > I can not disable too.- Hide quoted text -
>
> - Show quoted text -

thanks for your help, I looking for disable this interrupt on the net.