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Date: Tue, 18 May 2004 08:39:25 +0200
From: "Eli Zaretskii" <eliz AT gnu DOT org>
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To: djgpp AT delorie DOT com
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	(slavearcDOEDITWEG AT pandora DOT be)
Subject: Re: problem with DJGPP's make
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> From: "Lorenzo Dieryckx" <slavearcDOEDITWEG AT pandora DOT be>
> Newsgroups: comp.os.msdos.djgpp
> Date: Mon, 17 May 2004 18:57:38 GMT
> 
> Since my applications or libraries are in C++, I set gxx is my CC variable,

That's a mistake: for C++ programs, you should use CXX, not CC.

> but sometimes, make calles gpp instead, and also omits my include paths!!

If it calls gpp, it uses a built-in rule, because Make already knows
how to compile C++ source files.  That's why what DJ suggested worked.

You should use gpp as well, as gxx is not a fuill-fledged C++
compilation driver, it's just a wrapper around gcc, and thus does not
always know everything about the intimate details of C++ compilation,
like names and locations of libraries.

> Example:
> CC = gxx
> CFLAGS = -c

Use CXXFLAGS for C++ programs.  (The section "Catalogue of Rules" in
the Make manual lists all the rules that Make already knows about, so
if your case is only slightly different from one of those built-in
rules, all you need to do is fiddle a bit with one of the variables
that control that rule.)

> when I try to make this, I see this on the commandline:
> gpp        -c -o FileByteSource.o FileByteSource.cpp
> (notice the spaces between gpp and -c!)

Those spaces are because you didn't define CPPFLAGS and CXXFLAGS,
used by the built-in rule to copile C++ files.

> Of course, since the include paths are omited, the file fails to compile

Make uses a built-in rule here because a small typo in the rule you
tried to feed it:

> %.o : $(patsubst %.o, %cpp, $(OBJS)) $(HDRS)
>  $(CC) $(CCFLAGS) $(INCLUDE) $@ $<

There's a dot missing in "%cpp", it should have been "%.cpp".  Since
the resulting dependency doesn't match FileByteSource.cpp, Make
doesn't use this rule.

Also, you use $(CCFLAGS) while you defined $(CFLAGS).

Of course, as DJ pointed out, it's entirely redundant to try to craft
such a rule in the first place, since Make already knows how to
compile *.cpp files.

> Yet some other files which are quite similar compile without any problem!

That's because in this case, you have a rule

> $(OBJ) : $(SRC) $(HDR)
>  $(CC) $(CCFLAGS) $(INCLUDE) -o $@ $(SRC)

Which matches BinTreeNode.o and BinTreeNode.cpp exactly, so the rule
is used.