Message-ID: From: Prashant Ramachandra To: "'djgpp AT delorie DOT com'" Subject: RE: DJGPP timer slowdown Date: Wed, 31 Jan 2001 22:34:36 +0530 MIME-Version: 1.0 X-Mailer: Internet Mail Service (5.5.2650.21) Content-Type: text/plain Reply-To: djgpp AT delorie DOT com On Wednesday, January 31, 2001 10:03 PM, Alexei A. Frounze [SMTP:dummy_addressee AT hotmail DOT com] wrote: | > | If there's some code which runs upon timer interrupt and the number | of | instructions there varies from tick to tick, then if we measure time | using | BIOS tick counter, we end up with certain error due to that code | (SMARTDRV | is the case). Same thing with RDTSC - if any interrupt happens | between the | point we read the time (from BIOS tick counter or anything else) and | RDTSC | instruction and there's a lot of extra code in ISR, RDTSC gives us | an | adjusted value. These both things lead to a certain error in CPU | frequency | measurement unless we get a rid of all those interrupts and stuff | which | takes different amount of time. | This is the issue. The way I usually do this is to disable all interrupts and use the PIT to measure a short period of time. Get the TSC value before and after this loop. Then, the obvious calculations. That way you won't have to depend on the BIOS and it's pretty simple to do this, too. -- Prashant TR Web: http://www.midpec.com/ ********************************************************************** This email and any files transmitted with it are confidential and intended solely for the use of the individual or entity to whom they are addressed. If you have received this email in error please notify the system manager. This footnote also confirms that this email message has been swept by MIMEsweeper for the presence of computer viruses. www.mimesweeper.com **********************************************************************