From: M DOT A DOT Bukin AT inp DOT nsk DOT su
To: djgpp AT delorie DOT com
Subject: Re: An inline assembler RNG for C
References: <George Marsaglia's message of "Wed, 17 Feb 1999 13:35:29 -0500">  <36CB0BF1 DOT 23FF9E2 AT stat DOT fsu DOT edu> <3 DOT 0 DOT 6 DOT 32 DOT 19990218103218 DOT 008d7180 AT pop DOT globalserve DOT net> <20678zseao DOT fsf AT Sky DOT inp DOT nsk DOT su> <36CC8D02 DOT 3690E0EB AT stat DOT fsu DOT edu>
Date: 19 Feb 1999 08:45:20 +0600
In-Reply-To: George Marsaglia's message of "Thu, 18 Feb 1999 16:58:26 -0500"
Message-ID: <20pv77az7j.fsf@Sky.inp.nsk.su>
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Reply-To: djgpp AT delorie DOT com

George Marsaglia <geo AT stat DOT fsu DOT edu> writes:

> BUT  NOONE HAS YET SUGGESTED AN EASY
> INLINE ASSEMBLER SECTION OF CODE FOR THIS.
> SEVERAL RESPONDENTS SUGGESTED IT COULD
> BE DONE USING LONGLONG's, BUT ONLY A FEW PERCENT
> OF  CURRENT CPU's SEEM TO HAVE TRUE 64-BIT
> ARITHMETIC.

Do you mean that nobody suggested inline assembler for CPU's other
than i386?  Because my first post on this topic contained both inline
assembler, long long version and ANSI-C version (at least, nobody said
that it is not ANSI).  Code is after first question about sequence
degradation.  I am sure that in inline assembler I wrote, it is
possible to reduce amount of instructions (by using "m" constraints),
but I don't know how to write faster version.

BTW, question about seeding this RNG is still open.  I know at least
two sets of initial values that will lead to the sequence of the same
values.

x=0, c=0  and  x=(1<<n)-1, c=a-1  where n is number of bits (32 for
original algorithm).

-- 
Michael Bukin