Message-Id: <3.0.1.16.19970710101040.24c794b4@mailhost.sm.ic.ac.uk>
Date: Thu, 10 Jul 1997 10:10:40
To: djgpp AT delorie DOT com
From: Paul Dixon <p DOT dixon AT ic DOT ac DOT uk>
Subject: Re: Disabling cache?
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>On Tue, 8 Jul 1997, Johan Karlsson wrote:
>
>> I need to be able to turn the cache off for a specific memory area.
>> The memory board I'm using is a bit special, when I write to a specific
>> address I will affect all other addresses on the board. Therefor when I
>> read from the board a value stored in cache will not be valid.
>
>Did you actually see such problems?  AFAIK, the chipset on the 
>motherboard is usually smart enough to automatically disable caching of 
>addresses which are mapped to hardware devices.  So you shouldn't need 
>to do anything to have the desired effect.
>
>> Is there any way of turning the caching of for a specific address area?
>
>Only in the CMOS setup of your machine, if your setup has such an option.

This is totally untested and straight out of a book (The Intel Advanced
Microprocessors, B Brey 1993) but might help, FWIIW:

The _page_directory_ contains the location of up to 1024 page translation
tables, and can be located in memory addressed though control register CR3.
Each entry in this directory is 32 bits (4 bytes) and has a page table
address in bits 31-12, flags in the lower bits

b31 -------------- b12    b11-b9   b8 b7 b6 b5 b4  b3  b2 b1 b0
 address                  OS use   0  0  D  A  PCD PWT US RW P

D = dirty (used by OS)
A = accessed (set whenever accessed by microprocessor, used by OS)
PCD = page cache disabled 
PWT = page write-through
US = user / not supervisor
RW = writable / not read only
P = present

Each _page_table_ is 4k long, at a 4k aligned location in RAM, and is
addressed by one of the directory entries. It has a similar structure to
the directory except that the address in bits 31-12 is the physical address
of a 4k page of memory.

To convert a linear address (logical) to a physical address use  bits
b31-b22 as an offset into the page directory to find the address of a page
table. Then use b21-b12 as an offset into the page table to find entry for
page.

nb in V86 mode CR3 is different for each VM (ie each virtual machine can
have its own page tables) (this is likely to also be the case under NT but
I have no info).

So in principle it should be possible to access the page table entry (or
entries) that refer to your memory mapped device and set the cache disable
bits.

HOWEVER (big caveat ) I have no idea how the DPMI server would get in the
way of direct tampering with the page table... certainly NT is likely to
prevent write access to page tables from user privilege level ['ring 3'].


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Paul Dixon         http://www.sm.ic.ac.uk/paed/phps/pdixon/pdixon.htm

Software Engineer, Dept of Paediatrics  Telephone: (+44) 171 725 1098
St Mary's Hospital Medical School       Fax:       (+44) 171 725 6284
Norfolk Place, London W2 1PG, UK        Email:       p DOT dixon AT ic DOT ac DOT uk

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