Message-ID: From: Robert Humphris To: "'djGpp list'" Subject: MMX Date: Tue, 4 Mar 1997 10:18:19 -0000 Encoding: 49 TEXT I know that this is not related to the topic, but it may be something that should be thought about... MMX whatever is stands for ( I have heard several versions ) is the addition to the Pentium of some rather natty hardware, in the form of a SIMD parallel processing module. Single Instruction Multiple Data is basically the cheapest form of parallel processing to do, it means that multiple values can be processed at the same time, for instance: for( i=0; i<7; i++ ) { array[i] = array[i] ^ 20; } this would take eight iterations in a von Neuman architecture machine but only one in a SIMD machine ( as long as their is provision to take 8 values as there is in the MMX ). The result is huge speed up factors when performing tasks such as de/compressing, image processing, 3d image manipulation, etc. The question is, will DJGPP need to support this in the future? I think that it will, as the Parallel capability of future chips is going to be expanded upon MMX2 is already being tested, although what form this will take I do not know. Personal I think that it should be an extra set of C functions that provide the support, parallel scheduling, and optimization is still the stuff of Doctatorial reseach so I don't imagine that we will be seeing '-03SIMD' switches on the command line just yet, but I believe that we need to address the issue of how a set of parallel commands would be indicated ( is there any news from MS, Borland, or Watcom as to how they plan to do this? they will have had access to the chip for much longer than us ). We could go for something akin to that of Occam2 where the function : PAR( i=0; i<20; i++ ) indicates that the next 20 instructions are to be performed in parallel. Your thoughts/comments please Rob Humphris