Date: Wed, 8 Jun 94 09:12:57 EDT
From: hvb AT netrix DOT com
To: babcock AT cfa DOT harvard DOT edu
Cc: djgpp AT sun DOT soe DOT clarkson DOT edu, eliz AT is DOT elta DOT co DOT il
Subject: Memory mapped devices - question, help
Reply-To: hvb AT netrix DOT com

Dear all,

I am using go32 running on an 80486 system.  I have set up the CMOS to
have the cache disable for the memory address range to my memory map
device.  I, however, obtained inconsistent result while accessing data
from my memory map device.  Is that because I have not had the GDT
entry entries set up for those address ranges to disable the CPU
internal cache?  If this is required, how can I achieve that task?

Bob Babcock writes:
 > > Guarionex Morales wrote:
 > > >	 The memory mapped devices introduce yet another problem that I
 > > > have'nt seen mentioned in the list yet. For data integrity,
 > > > caching has to be disabled for the memory area where the device is
 > > > mapped onto.
 > > 
 > 
 > CMOS setup programs sometimes let you select which memory areas in the
 > A000-FFFF range are cacheable or shadowable, and these setting may be
 > critical in determining whether a peripheral will work.  The more interesting
 > case is a device with memory beyond the first MB.  I don't really know how
 > these work with a cache, but as you say, they must have a way of invalidating
 > the cache or they wouldn't work at all.

Thanks,
==============================================================
Hung Bui                           Internet: hvb AT netrix DOT com
Netrix Corporation                    Phone: +1 703 793 1016
13595 Dulles Technology Drive           Fax: +1 703 713 3805
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