To: Guarionex Morales <morales AT buphyk DOT bu DOT edu>
Cc: djgpp AT sun DOT soe DOT clarkson DOT edu
Subject: Re: Memory mapped devices 
Date: Mon, 23 May 94 10:33:07 +0300
From: eliz AT is DOT elta DOT co DOT il

Guarionex Morales wrote:
>	 The memory mapped devices introduce yet another problem that I
> have'nt seen mentioned in the list yet. For data integrity,
> caching has to be disabled for the memory area where the device is
> mapped onto.

  There is a good reason you didn't see this on the list: the problem does not
exist.  Motherboard manufacturers did already take (hopefully good) care of
this by DISABLING the cache automagically when reading from the address range
where memory-mapped devices usually sit (on a PC, this would be A000 - FFFF).
It must be this way, because otherwise no memory-mapped device would work, as
programs usually don't distinguish between memory located on the motherboard
vs on a periferal card.  In an environment where memory mapping is used (such
as V86 [virtual-8086] mode, which everybody running EMM, QEMM and the like uses),
this is next to impossible, because the program never sees the physical address.
So, for the periferal cards to work, the cache MUST be disabled transparently
when a certain range of PHYSICAL addresses is accessed by the CPU.  These
addresses must be treated as if they were `volatile' variables whose value
might change any time; thus they can't be cached.

So much for the theory.  As to the facts, I don't know exactly how they achieve
this through the motherboard design, but I have an evidence to the validity of
the above:

   I've wrote and timed a program which reads blocks of data from a periferal
device (I used VGA video RAM and a memory-mapped A/D card for these tests). The
program was run once by moving a source pointer by 8K on each iteration
so that the values in the cache couldn't be used, and another time without
moving the pointer.  Guess what? the results were IDENTICAL.  (For the record:
the VGA and the A/D card both sit on the AT bus, not VL-bus, so using cached
values would be MUCH faster.)  This was tested both with and without the
external (so called L2) cache, with same results.  Conclusion: the PC somehow
"knew" it was accessing a periferal and disabled the cache.

   Also, if I recall correctly, the chips that sit in the core of motherboard
chip-sets have special provisions for invalidating cache for certain address
ranges.  Can't remember now, what chips do, but I clearly remember seeing this
on data sheets of some such.

	Eli Zaretskii