Date: Sun, 13 Jun 1999 11:21:08 +0300 (IDT)
From: Eli Zaretskii <eliz AT is DOT elta DOT co DOT il>
X-Sender: eliz AT is
To: Robert Hoehne <robert DOT hoehne AT gmx DOT net>
cc: djgpp-workers AT delorie DOT com
Subject: Floating point info in GDB 4.18
Message-ID: <Pine.SUN.3.91.990613112019.17906P-100000@is>
MIME-Version: 1.0
Content-Type: TEXT/PLAIN; charset=US-ASCII
Reply-To: djgpp-workers AT delorie DOT com


The following changes to GDB's go32-nat.c solve several minor problems
with reporting FPU-related info:

  - CS:EIP of the last FP instruction and DS:offset of the operand
    were printed incorrectly by "info registers" due to wrong order in
    regno_mapping[];
  - FP registers were printed by "info float" in the wrong order,
    since FNSAVE saves them in TOP-relative order, not in physical
    order;
  - FP registers' contents were printed in the wrong byte order, and
    also the last 2 of the 10 bytes were not printed at all.

I also made the following small changes:

  - FP registers are now printed beginning with R7 down to R0 instead
    of the other way around, since this is how all other i386-based
    targets display them.
  - I changed "trap" to "special" in the interpretation of the tag
    word, because that's how Intel manuals call it (FSDB also uses
    "special", btw), and I think "trap" is misleading anyway.


*** gdb/go32-nat.c~7	Sat Jun  5 19:58:40 1999
--- gdb/go32-nat.c	Sat Jun 12 12:16:54 1999
*************** print_387_status (unsigned short status,
*** 233,265 ****
  
    top = (ep->status >> 11) & 7;
  
!   printf_unfiltered ("regno tag   msb          lsb  value\n");
!   for (fpreg = 0; fpreg < 8; fpreg++)
      {
        long double val;
  
        printf_unfiltered ("%s %d: ", fpreg == top ? "=>" : "  ", fpreg);
  
        switch ((ep->tag >> (fpreg * 2)) & 3)
  	{
  	case 0:
! 	  printf_unfiltered ("valid ");
  	  break;
  	case 1:
! 	  printf_unfiltered ("zero  ");
  	  break;
  	case 2:
! 	  printf_unfiltered ("trap  ");
  	  break;
  	case 3:
! 	  printf_unfiltered ("empty ");
  	  break;
  	}
!       for (i = 0; i < 8; i++)
! 	printf_unfiltered ("%02x", ep->regs[fpreg][i]);
  
!       REGISTER_CONVERT_TO_VIRTUAL (FP0_REGNUM + fpreg, builtin_type_long_double,
! 				   &ep->regs[fpreg], &val);
  
        printf_unfiltered ("  %LG\n", val);
      }
--- 233,274 ----
  
    top = (ep->status >> 11) & 7;
  
!   printf_unfiltered ("regno tag     msb              lsb  value\n");
!   for (fpreg = 7; fpreg >= 0; fpreg--)
      {
+       /* FNSAVE saves the FP registers in their logical TOP-relative
+ 	 order, beginning with ST(0).  Since we need to print them in
+ 	 their physical order, we have to remap them.  */
+       int  regno = fpreg - top;
        long double val;
  
+       if (regno < 0)
+ 	regno += 8;
+ 
        printf_unfiltered ("%s %d: ", fpreg == top ? "=>" : "  ", fpreg);
  
        switch ((ep->tag >> (fpreg * 2)) & 3)
  	{
  	case 0:
! 	  printf_unfiltered ("valid   ");
  	  break;
  	case 1:
! 	  printf_unfiltered ("zero    ");
  	  break;
  	case 2:
! 	  /* All other versions of print_387_status use TRAP here, but I
! 	     think this is misleading, since Intel manuals say SPECIAL.  */
! 	  printf_unfiltered ("special ");
  	  break;
  	case 3:
! 	  printf_unfiltered ("empty   ");
  	  break;
  	}
!       for (i = 9; i >= 0; i--)
! 	printf_unfiltered ("%02x", ep->regs[regno][i]);
  
!       REGISTER_CONVERT_TO_VIRTUAL (FP0_REGNUM+regno, builtin_type_long_double,
! 				   &ep->regs[regno], &val);
  
        printf_unfiltered ("  %LG\n", val);
      }
*************** regno_mapping[] =
*** 304,316 ****
    5, 10,
    6, 10,
    7, 10,
    0, 2,			/* control word, from npx */
    4, 2,			/* status word, from npx */
    8, 2,			/* tag word, from npx */
-   12, 4,		/* last FP exception EIP from npx */
    16, 2,		/* last FP exception CS from npx */
!   20, 4,		/* last FP exception operand offset from npx */
!   24, 2			/* last FP exception operand selector from npx */
  };
  
  static struct
--- 313,327 ----
    5, 10,
    6, 10,
    7, 10,
+ 	/* The order of the next 7 registers must be consistent
+ 	   with their numbering in config/i386/tm-go32.h, which see.  */
    0, 2,			/* control word, from npx */
    4, 2,			/* status word, from npx */
    8, 2,			/* tag word, from npx */
    16, 2,		/* last FP exception CS from npx */
!   24, 2,		/* last FP exception operand selector from npx */
!   12, 4,		/* last FP exception EIP from npx */
!   20, 4			/* last FP exception operand offset from npx */
  };
  
  static struct