Message-Id: Date: Wed, 31 Jul 1996 10:28:44 +1200 From: Bill Currie To: djgpp-workers AT delorie DOT com Subject: djasm patch - more instructions I've added more instructions to djasm: j(e)cxz, setcc, ret(f)d, sal, jmpf abslolue, .org with fill. I think that's all my mods. BTW, regmem doesn't seem to allow registers (which is good for setcc). Is this behavioure caused by precedence and the need for the '%expect 2' line? --------------cut------------------- *** /djgpp/src/stub/djasm.y Thu Jul 25 15:36:16 1996 --- djasm.y Tue Jul 30 13:00:52 1996 *************** *** 174,180 **** %token NUMBER REG8 REG16 REG32 SREG STRING PC CRREG DRREG TRREG %token ARITH2 ARITH2B ARITH2D ARITH2W %token LXS MOVSZX ! %token JCC JCCL LOOP %token SHIFT SHLRD %token ONEBYTE TWOBYTE ASCADJ %token BITTEST GROUP3 GROUP3B GROUP3D GROUP3W GROUP6 GROUP7 --- 174,180 ---- %token NUMBER REG8 REG16 REG32 SREG STRING PC CRREG DRREG TRREG %token ARITH2 ARITH2B ARITH2D ARITH2W %token LXS MOVSZX ! %token JCC JCCL JCXZ LOOP SETCC %token SHIFT SHLRD %token ONEBYTE TWOBYTE ASCADJ %token BITTEST GROUP3 GROUP3B GROUP3D GROUP3W GROUP6 GROUP7 *************** *** 189,195 **** %token IMUL IMULB IMULD IMULW %token ORG OUT %token POP POPW POPD PUSH PUSHW PUSHD ! %token RCS_ID RET RETF %token STACK START %token TEST TESTB TESTD TESTW TYPE %token XCHG --- 189,195 ---- %token IMUL IMULB IMULD IMULW %token ORG OUT %token POP POPW POPD PUSH PUSHW PUSHD ! %token RCS_ID RET RETF RETD RETFD %token STACK START %token TEST TESTB TESTD TESTW TYPE %token XCHG *************** *** 402,407 **** --- 402,410 ---- "jnlel", JCCL, 15, "jgl", JCCL, 15, + "jcxz", JCXZ, 0, + "jecxz", JCXZ, 1, + "jmp", JMPB, NO_ATTR, "jmpf", JMPF, NO_ATTR, "jmpl", JMPW, NO_ATTR, *************** *** 446,452 **** --- 449,457 ---- "rcl", SHIFT, 2, "rcr", SHIFT, 3, "ret", RET, NO_ATTR, + "retd", RETD, NO_ATTR, "retf", RETF, NO_ATTR, + "retfd", RETFD, NO_ATTR, "rol", SHIFT, 0, "ror", SHIFT, 1, "sar", SHIFT, 7, *************** *** 454,462 **** --- 459,500 ---- "sbbb", ARITH2B, 3, "sbbd", ARITH2D, 3, "sbbw", ARITH2W, 3, + + "seto", SETCC, 0, + "setno", SETCC, 1, + "setb", SETCC, 2, + "setc", SETCC, 2, + "setnae", SETCC, 2, + "setnb", SETCC, 3, + "setnc", SETCC, 3, + "setae", SETCC, 3, + "setz", SETCC, 4, + "sete", SETCC, 4, + "setnz", SETCC, 5, + "setne", SETCC, 5, + "setbe", SETCC, 6, + "setna", SETCC, 6, + "setnbe", SETCC, 7, + "seta", SETCC, 7, + "sets", SETCC, 8, + "setns", SETCC, 9, + "setp", SETCC, 10, + "setpe", SETCC, 10, + "setnp", SETCC, 11, + "setpo", SETCC, 11, + "setl", SETCC, 12, + "setnge", SETCC, 12, + "setnl", SETCC, 13, + "setge", SETCC, 13, + "setle", SETCC, 14, + "setng", SETCC, 14, + "setnle", SETCC, 15, + "setg", SETCC, 15, + "sgdt", GROUP7, 0, "sidt", GROUP7, 1, "sldt", GROUP6, 0, + "sal", SHIFT, 4, "shl", SHIFT, 4, "shld", SHLRD, 0xa4, "shr", SHIFT, 5, *************** *** 684,692 **** --- 722,733 ---- | JCC ID { emitb(0x70+$1); emits($2,0,REL_8); $2->type |= SYM_code; } | JCCL ID { emitb(0x0f); emitb(0x80+$1); emits($2,0,REL_16); $2->type |= SYM_code; } + | JCXZ ID { if ($1) emitb(0x66); emitb(0xe3); emits($2,0,REL_8); $2->type |= SYM_code; } + | JMPW ID { emitb(0xe9); emits($2,0,REL_16); $2->type |= SYM_code; } | JMPB ID { emitb(0xeb); emits($2,0,REL_8); $2->type |= SYM_code; } | JMPF regmem { emitb(0xff); reg(5); } + | JMPF const ':' constID { emitb(0xea); emits($4.sym,$4.ofs,REL_abs); emitw($2); } | LINKCOFF STRING { strbuf[strbuflen]=0; do_linkcoff(strbuf); } | LOOP ID { emitb($1); emits($2,0,REL_8); } *************** *** 758,763 **** --- 799,805 ---- | MOVSZX REG32 ',' REG16 { emitb(0x66); emitb(0x0f); emitb($1+1); modrm(3, $2, $4); } | ORG const { if (pc > $2) yyerror ("Backwards org directive"); else while (pc < $2) emitb(0x90); } + | ORG const ',' const { if (pc > $2) yyerror ("Backwards org directive"); else while (pc < $2) emitb($4); } | OUT const ',' REG8 { emitb(0xe6); emitb($2); } | OUT const ',' REG16 { emitb(0xe7); emitb($2); } *************** *** 783,788 **** --- 825,837 ---- | RET const { emitb(0xc2); emitw($2); } | RETF { emitb(0xcb); } | RETF const { emitb(0xca); emitw($2); } + | RETD { emitb(0x66); emitb(0xc3); } + | RETD const { emitb(0x66); emitb(0xc2); emitd($2); } + | RETFD { emitb(0x66); emitb(0xcb); } + | RETFD const { emitb(0x66); emitb(0xca); emitd($2); } + + | SETCC REG8 { emitb(0x0f); emitb(0x90+$1); modrm(3, 0, $2); } + | SETCC regmem { emitb(0x0f); emitb(0x90+$1); reg(0); } | SHIFT REG8 ',' const { emitb($4 == 1 ? 0xd0 : 0xc0); modrm(3, $1, $2); if ($4 != 1) emitb($4); } | SHIFT REG8 ',' REG8 { if ($4 != 1) yyerror ("Non-constant shift count must be `cl'"); emitb(0xd2); modrm(3, $1, $2); }