Message-Id: <200006230948.MAA02794@mailgw1.netvision.net.il>
Date: Fri, 23 Jun 2000 12:49:14 +0200
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From: "Eli Zaretskii" <eliz AT is DOT elta DOT co DOT il>
To: djgpp AT delorie DOT com
In-reply-to: <395309A1.881A2311@pacbell.net> (message from Wesel on Thu, 22
	Jun 2000 23:54:25 -0700)
Subject: Re: Make file wildcards
References:  <395309A1 DOT 881A2311 AT pacbell DOT net>
Reply-To: djgpp AT delorie DOT com
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> From: Wesel <nospam AT pacbell DOT net>
> Newsgroups: comp.os.msdos.djgpp
> Date: Thu, 22 Jun 2000 23:54:25 -0700
>
> The makefile suggested by the good people at delorie.com went as
> follows:
> --------------------------------------------------------
> CC = gcc
> CFLAGS = -g -O2
> OBJECTS = main.o foo.o
> 
> main.exe : $(OBJECTS)
>         $(CC) $(CFLAGS) $(OBJECTS) -o main.exe
> 
> %.o : %.c
>         $(CC) $(CFLAGS) -c $<
> --------------------------------------------------------

Unfortunately, the good people at delorie.com were slightly misleading
or mistaken ;-).

> I built my makefile as follows:
> 
> --------------------------------------------------------
> CC = gcc
> CFLAGS = -g
> OBJECTS = test.o
> 
> main.exe : $(OBJECTS)
> 	$(CC) $(CFLAGS) $(OBJECTS) -o main.exe
> 
> %.o : %.c %.cpp %.h
> 	$(CC) $(CFLAGS) -c $<
> --------------------------------------------------------
> 
> My hopes were that upon discovering a modified .cpp file, make would
> compile test.o then, finding a modified (created) test.o file, it would
> build main.exe from the object file.  The makefile compiled fine, but it
> used a sneaky implicit rule.  Apparantly %.o : %.cpp is built-in, so
> what I saw was
> 
> --------------------------------------------------------
> make -k
> gpp    -c -o test.o test.cpp
> gcc -g test.o -o main.exe

This is expected behavior.  As written, the implicit rule you used
is just another implicit rule, not unlike the one that Make already
knows about.  When Make sees more than one implicit rule to build the
same target, it chooses the first one, which will always be the one
that's built into Make.

Lesson no.1: do not use implicit rules if Make already has a built-in
rule for that case.  Instead, tailor the existing implicit rule to
your need by changing the variables used by that rule, such as CC,
CXX, CXXFLAGS, etc.

To get Make do what you want, use a static pattern rule instead of an
implicit rule, like this:

$(OBJECTS):  %.o : %.c %.cpp %.h

The addition of "$(OBJECTS)" makes all the difference you need.  For
more about this, read the node "Static versus Implicit" in the Make
manual.

> Compilation finished at Thu Jun 22 20:29:34

Kudos on using Emacs ;-)

> Is there any way I can use wildcards with the make utility provided by
> djgpp?

Yes, you can, but I'm not sure in what context would you need that, so
I cannot give specific advice.  You may wish to read the node
"Wildcards" in the Make manual.