From: kagel AT quasar DOT bloomberg DOT com
Date: Thu, 9 May 1996 16:40:03 -0400
Message-Id: <9605092040.AA05326@quasar.bloomberg.com >
To: lav AT video DOT yars DOT free DOT net
Cc: j DOT aldrich6 AT genie DOT com, djgpp AT delorie DOT com
In-Reply-To: <199605091525.TAA16776@video.yars.free.net> (lav@video.yars.free.net)
Subject: Re:  more sizeof questions
Reply-To: kagel AT dg1 DOT bloomberg DOT com

   Errors-To: postmaster AT ns1
   Date: Thu, 9 May 1996 19:25:13 +0400 (MSD)
   From: "Alexander V. Lukyanov" <lav AT video DOT yars DOT free DOT net>
   Cc: djgpp AT delorie DOT com
   Content-Type: text
   Content-Length: 1343

   > From: kagel AT quasar DOT bloomberg DOT com
   > j DOT aldrich AT genie DOT com responded on 05/08/96 3:15 UTC
   > 
   >    Each of your 2-byte fields gets another 2 bytes of padding on it, for
   >    a total of 260.  There IS a workaround, though, in the form of the gcc
   >    __attribute__ ((packed)) command.  See my last post for details.
   > 
   > Not quite.  Actually, each field does NOT need word-alignment.  Only objects
   > whose size is >= 4 bytes (long, int, float, long long & double [did I miss
   > any?]) require word (4byte) address alignment.  The member TotalMemory is not
   > padded as both it and the char array Info require 2byte alignment.  The extra
   > two bytes are added at the end of the structure to insure that each element of
   > an array of _VGAInfoBlock's will each have their first member, VESASignature,
   > aligned.

   IMHO, only char is never aligned. Any field crossing 4-byte memory boundary
   should be aligned at the boundary, so it can be fetched from memory at once.
   If a field is larger than 4 bytes, then it should be aligned so that it
   crosses not more than (size-1)/4 such boundaries.

You mis-read me, or I was not clear.  I said that each field does not need WORD
alignment (meaning 4byte machine words not the poster's artificial 2byte word).
Indeed, Intel processors require that objects sized < 4 bytes be aligned
according to their size, ie bytes are byte aligned (or non-aligned if you
prefer), short ints are 1/2word aligned, if there were a 3byte int it would
require 3byte alignment.  Objects sized at 4 bytes or larger require word
alignment.  Contrast this with the Motorolla 88XX0 series which requires object
size alignment for all primitive objects such that doubles require double word
alignment.  And wait for 64-bit processors to REALLY screw up structure
alignment!


   The reasin for that is memory ability to retrieve only aligned words,
   so if a word crosses 4-byte boundary processor actually need to retrieve
   two words, that take more time of course.

   Some processors (mostly RISC, IMHO) can't retrieve not aligned words at all.

Right, witness the 88XX0 processors, but compilers for these CPUs all have
option flags to permit mis/unaligned objects by generating temp vars and copy
code at the cost of varying loss of execution speed.

-- 
Art S. Kagel, kagel AT quasar DOT bloomberg DOT com

A proverb is no proverb to you 'till life has illustrated it.  -- John Keats