Date: Thu, 11 Jan 1996 17:57:16 -0500
To: djgpp AT delorie DOT com
From: Dave Montgomery <dmont AT tradeit DOT com>
Subject: makefile (how they vex me)

I'm having a couple of problems with makefiles.  First, I'd like
to arrange the hierarchy as follows:

   .              makefile, .EXE, some .BAT files etc.
   .\SRC          *.CPP, *.H
   .\OBJ          *.O
   .\DEP          *.D

I've gotten as far as the following makefile
-----
# I like the trailing slash so that if I don't define one of the
# directories, the names will go unchanged.
OBJ_DIR = OBJ/
SRC_DIR = SRC/
DEP_DIR = DEP/

# gcc finds the includes and source OK
vpath %.h   $(SRC_DIR)
vpath %.cpp $(SRC_DIR)
vpath %.o   $(OBJ_DIR)

# the objects are generated in OBJ
%.o : %.cpp
    gcc -c $< -o $(OBJ_DIR)$@

# first problem I can't redirect to DEP/$@ since / is not the correct
# character in DOS.  I can change all of the slashes above to double
# backslashs \\ which works (but generates REALLY ugly names, just try it)
%.d : %.cpp
    gcc -MM $< | sed "s/$*.o/& $@/g" > $(DEP_DIR)$@

SRC := file1.cpp file2.cpp

DEPS := $(SRC:.cpp=.d)
OBJS := $(SRC:.cpp=.o)

FULL_DEPS := $(addprefix $(DEP_DIR), $(DEPS))
FULL_OBJS := $(addprefix $(OBJ_DIR), $(OBJS))

# here's the problem, if I put $(OBJS) then we're looking in the
# current directory (regardless of above vpath).  if I put $(FULL_OBJS)
# then I get a 'no rule to make target OBJ/file.o
myprog: $(OBJS)
    gcc -o $@ $(FULL_OBJS) -lgpp -lpc -lm

# I have similar problems with the include of $(DEPS) and $(FULL_DEPS)
include $(FULL_DEPS)
-----

Any ideas????

Thanks in advance.

Regards,
   Dave Montgomery
---
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