Date: Fri, 2 Dec 1994 13:22:40 +0100
From: gbm AT ii DOT pw DOT edu DOT pl (Grzegorz B. Mazur)
To: djgpp AT sun DOT soe DOT clarkson DOT edu
Subject: 486 help wanted


Excuse me for putting non-djgpp related mail on the list, but there are so many
messages that I hope this will not bother you :-).

Can anyone give me some info or point to internet-reachable source of info on the following topic (please do not write that I can obtain it after signing the 
agreement with Intel...).

A friend of mine is writing a cache test program for 486. (It is a part of
his MSc project). 486 contains several TestRegisters for this purpose, and
their contents and functions are well documented in the manual. There is only
one problem: you cannot write anything to TR5...
OK, no EMM386 or any other CPU masters, just plain real mode.
There is a testing procedure source in Intel manual, and the comment at the
beginning of it says that "access to tr5 should be enabled in cr0 prior to
executing the code". Does it mean that there is an undocumented bit in cr0
enabling the access to tr5?

Any help will be appreciated.

Gregory