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Date: Thu, 26 Feb 2026 18:04:43 -0800 (PST)
To: Eliot Moss <moss AT cs DOT umass DOT edu>,
        Dimitry Andric <dimitry AT unified-streaming DOT com>
Cc: KENNON J CONRAD via Cygwin <cygwin AT cygwin DOT com>
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Subject: Re: Memmove causing program crashes, giving SIGTRAP in GDB(?)
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Perhaps something like this?  Maybe I need to try a BIOS update?

Intel Haswell (and related architectures) processors may experience stability issues, including machine check errors (MCEs), due to a microcode bug related to REP MOVS (specifically REP MOVSB or REP MOVSQ) handling. These issues often cause system crashes or lockups, leading to microcode, BIOS/UEFI updates to resolve them. 
Debian Wiki
 +4
Issue: A high-rate of interrupts or specific memory operations can cause REP MOVS instructions to trigger Machine Check Errors (MCE) or internal errors (IERR) on older processors.
Affected Processors: The bug primarily impacts older Intel processors, including Haswell and Broadwell architectures.
Fix/Mitigation: The primary solution is to apply the latest motherboard BIOS/UEFI update, which contains the corrected microcode update (often labelled 20180108 or later).
Background: This is linked to Intel’s efforts to fix security vulnerabilities (like Spectre), where early patches for Haswell/Broadwell caused unexpected instability, requiring further refinements. 
Debian Wiki
 +4

-Kennon

> On 02/26/2026 2:30 PM PST Eliot Moss <moss AT cs DOT umass DOT edu> wrote:
> 
>  
> I know it's a low probability for a cause, but I wonder if either the
> hardware or the OS have some issue with proper restartability of the
> REP MOVSQ under some weird circumstance.  If the hardware/firmware
> does not save the in-flight register information correct (again, in
> some weird and rare situation) then restarting the instruction could
> fail.  Might be worth:
> 
> (a) trolling the web to see if there are reports of issues around this
>      instruction, Intel firmware fixes, etc.  (An instruction like REP
>      MOVSQ is almost certainly implemented with a microcode loop, etc.)
> 
> (b) trying this exact code with a substantially different CPU model
>      (which might tend to avoid any microcode bug in the model you're
>      using).
> 
> Again, low probability, but ...
> 
> Regards - EM

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