DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 14F693858D28
To: cygwin AT cygwin DOT com
Date: Sat, 08 Apr 2023 15:33:49 -0600
Message-Id: <announce.20230408153349.41037-1-Brian.Inglis@Shaw.ca>
Subject: [ANNOUNCEMENT] Updated: cpuid 20230406
From: Cygwin cpuid Maintainer via Cygwin-announce via Cygwin
 <cygwin AT cygwin DOT com>
Reply-To: cygwin AT cygwin DOT com
Cc: Cygwin cpuid Maintainer via Cygwin-announce <cygwin-announce AT cygwin DOT com>,
        Cygwin cpuid Maintainer <Brian DOT Inglis AT Shaw DOT ca>
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
Sender: "Cygwin" <cygwin-bounces+archive-cygwin=delorie DOT com AT cygwin DOT com>

The following package has been upgraded in the Cygwin distribution:

* cpuid		20230406

Displays detailed information about the CPU(s) gathered from the
CPUID instruction, and also determines the exact model of CPU(s).
Where /proc/cpuinfo shows features important to a system, cpuid shows
what every feature in each CPU's architecture does.
It is updated and released frequently to stay current with Intel and
AMD information and supports other vendors' chips.

See the project home page for more information:

	http://etallen.com/cpuid.html

For information about changes since the previous Cygwin release,
see below or /usr/share/doc/cpuid/ChangeLog after installation.


Thu Apr  6 2023		20230406

Based on Intel-Linux-Processor-Microcode-Data-Files (ILPMDF*),
made the following (synth) changes: cpuid.c:

- Fixed bug in print_apic_synth() when interpreting leaf 0xb and 0x1f
  bit widths: In fact, they are bit *offsets*, different from the
  *widths* of leaf 4! So the (APIC width synth) often has been off by 1,
  and the (APIC synth) PKG_ID & CORE_ID values often have been shifted
  incorrectly.
- For 0xb/*/eax & 0x1f/*/eax, rename field to "bit width of level &
  previous levels" to reflect this definition.
- In print_apic_synth(), decode_mp_synth(), and print_mp_synth(),
  support APIC bit fields for the newest 4 topology layers: module,
  tile, die, die group. And for the mp version, also the older cu & pkg
  levels.
- In print_apic_synth(), use the extended APIC ID's when available in a
  variety of leaves.
- In print_apic_synth() & decode_mp_synth(), support leaf 0xb method for
  AMD/Hygon.
- In decode_mp_synth(), for the 1/0x80000008 method, use the same
  family-specific technique to differentiate CU's from cores, or cores
  from threads as in print_apic_synth().

- Added prelim Bergamo A1 stepping from sample from @YuuKi_AnS.
- Added 7/1/edx AMX-COMPLEX instructions.
- Added 7/2/edx UC-lock disable.
- Added 0x10/n/ecx non-contiguous 1s value supported.
- Added 0x1c/ecx event logging supported bitmap.
- Added 0x23/0/ebx decoding.
- Decode 0x80000026/1/ebx core type & native model.
- For 0x80000021/eax, capitalize REP STOSB & REP CMPSB to match Intel
  versions in 7/1/eax.
- For 0x80000022/ecx, shorten description, show bitmask only in hex.
- Update CPUID utility with new feature bits as documented in the AMD
  Processor Programming Reference for Family 19h and Model 11h:
  0x8000000a/edx extended LVT offset fault change
  0x80000021/eax enhanced predictive store forwarding, FSRS, FSRC,
		 FsGsKernelGsBaseNonSerializing
  0x80000022/ebx number of available UMC PMCs
  0x80000022/ecx bitmask representing active UMCs
- Differentiate preliminary (uarch synth) for (0,6),(10,10);
  (0,6),(10,11); (0,6),(10,12); and (0,6),(11,5) Crestmont Atom cores
  from their Redwood Cove counterparts.
- Add preliminary (synth) & (uarch synth) for (0,6),(12,6) Lion Cove &
  Skymont, from LX*.
- Added 12/0/eax SGX ENCLS EUPDATESVN bit.
- Added 0x1f/*/ecx level type value "die group (6)".
- Added (synth) decoding for (0,6),(8,15) Sapphire Rapids D & E0
  steppings from coreboot*.
- Improved (synth) decoding for (0,6),(6,10) Scalable 3rd Gen Xeons to
  Ice Lake-SP. Also, improved decoding for engr samples where the brand
  string omits Xeon & Bronze/Silver/Gold/Platinum.
- Improved (synth) decoding for (0,6),(11,14) Intel N-Series.
- Differentiate (synth) & (uarch synth) for (0,6),(11,14) Alder Lake-N
  based on core type, much like for other Alder Lake models. This
  corrects the cores to Gracemont. As for Golden Cove, perhaps P-cores
  never will exist for this model but, if they do, they should now be
  decoded correctly.
- Updated (synth) decoding for (0,6),(11,15),5 with Raptor Lake-S/HX/P.
- Updated (synth) decoding for (0,6),(11,10) with Raptor Lake-H/U/P.

- cpuid.man: Added 759603: Intel Processor and Intel Core i3 N-Series
  Datasheet, Volume 1 of 2.


-- 
Problem reports:      https://cygwin.com/problems.html
FAQ:                  https://cygwin.com/faq/
Documentation:        https://cygwin.com/docs.html
Unsubscribe info:     https://cygwin.com/ml/#unsubscribe-simple