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To: cygwin AT cygwin DOT com
Date: Sat, 04 Mar 2023 11:14:34 -0700
Message-Id: <announce.20230304111434.11956-1-Brian.Inglis@Shaw.ca>
Subject: [ANNOUNCEMENT] Updated: cpuid 20230228
From: Cygwin cpuid Maintainer via Cygwin-announce via Cygwin
 <cygwin AT cygwin DOT com>
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        Cygwin cpuid Maintainer <Brian DOT Inglis AT Shaw DOT ca>
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The following package has been upgraded in the Cygwin distribution:

* cpuid		20230228

Displays detailed information about the CPU(s) gathered from the
CPUID instruction, and also determines the exact model of CPU(s).

Whereas /proc/cpuinfo is like an abstract of the features important to
Linux in a system, cpuid is a standalone utility which writes a paper
expounding on every feature in each CPU's architecture and what it can
do, at about the one line per bit level.

It is updated and released frequently to stay current with Intel and
AMD information and supports other vendors' chips.

See the project home page for more information:

	http://etallen.com/cpuid.html

For information about changes since the previous Cygwin release,
see below or /usr/share/doc/cpuid/ChangeLog after installation.


Tue Feb 28 2023		20230228

* cpuid.man: Added Intel Flexible Return and Event Deliver (FRED).

* cpuid.c:

  - Corrected 7/1/eax fast REP instructions, where I'd left the REP prefix
    out of the description.
  - Added 7/1/eax FRED & LKGS bits, from Intel Flexible Return and Event
    Deliver (FRED).
  - Clarified 7/1/eax ArchPerfmonExt, which indicates that leaf 0x23 is
    valid.
  - Added (uarch synth) decoding for AMD Ryzen (Phoenix E0), based on
    sample from bakerlab.org, which I missed on Oct 3 2022, when I added
    the (synth) decoding.
  - Added 0x80000001/ebx PkgType decoding for AMD (10,15) Family 19h CPUs:
    (2,1) Vermeer, (5,1) Cezanne/Barcelo, (6,1) Raphael, and (7,0)
    Phoenix, based on their respective PPPR's.
  - Added very early (synth) decoding for Lunar Lake.  There is no
    corresponding (uarch synth) decoding, because no name is yet known for
    the uarch.
  - Added (0,6),(9,10) Alder Lake Core names: i*-12000.
  - Differentiate (0,6),(9,7) & (0,6),(9,10) Alder Lake Gracemont E-cores
    from Golden Cove P-cores.
  - Differentiate (0,6),(11,7); (0,6),(11,10) & (0,6),(11,15) Raptor Lake
    Gracemont E-cores from Raptor Cove P-cores.
  - Added (synth) & (uarch synth) decoding for (10,15),(7,8) Phoenix 2,
    from Coreboot*.
  - Renamed print_hypervisor_3_eax_xen to print_hypervisor_3_0_eax_xen.
  - Added print_hypervisor_3_0_ebx_xen and decode Xen tsc mode.
  - Added (synth) decoding for (10,15),(6,1,1) Raphael B1.


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