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To: cygwin AT cygwin DOT com
Date: Sat, 21 Jan 2023 16:01:41 -0700
Message-Id: <announce.20230121160141.34629-1-Brian.Inglis@Shaw.ca>
Subject: [ANNOUNCEMENT] Updated: cpuid 20230120
From: Cygwin cpuid Maintainer via Cygwin-announce via Cygwin
 <cygwin AT cygwin DOT com>
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        Cygwin cpuid Maintainer <Brian DOT Inglis AT Shaw DOT ca>
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The following package has been upgraded in the Cygwin distribution:

* cpuid		20230120

Displays detailed information about the CPU(s) gathered from the
CPUID instruction, and also determines the exact model of CPU(s).

Whereas /proc/cpuinfo is like an abstract of the features important to
Linux in a system, cpuid is a standalone utility which writes a paper
expounding on every feature in each CPU's architecture and what it can
do, at about the one line per bit level.

It is updated and released frequently to stay current with Intel and
AMD information and supports other vendors' chips.

See the project home page for more information:

	http://etallen.com/cpuid.html

For information about changes since the previous Cygwin release,
see below or /usr/share/doc/cpuid/ChangeLog after installation.


Fri Jan 20 2023		20230120

- Eliminate reliance on "old" build system. Instead, for the cpuid.i386
  and cpuid.x86_64, meant to be executable anywhere, including on old
  hardware & distros, use static builds. They're much bigger, but
  utterly immune to library changes.
- Intel's 13th Generation Core datasheet provides stepping names as well
  as numbers! So:
- Added synth decoding for (0,6),(11,7) Raptor Lake B0 stepping.
- Added synth decoding for (0,6),(11,15) Raptor Lake C0 steppings, and
  clarified case for unknown stepping.
- cpuid.man: Added 743844: 13th Generation Core datasheet.
- Fixed (0,6)(12,15) synth typo: Emerald Rapids.
- Added 6/eax IA32_HW_FEEDBACK_THREAD_CONFIG bit 25.
- Added 7/0/edx SGX-KEYS: SGX attestation services.
- Clarified 7/0/edx IA32_MCU_OPT_CTRL SRBDS mitigation MSR.
- Clarified 7/0/edx IA32_TSX_FORCE_ABORT MSR.
- Added 7/1/edx CET_SSS: shadow stacks w/o page faults.
- Added several 7/2/edx bits.
- In 0xd/0/eax, corrected CET_U & CET_S, which were IA32_XSS.
- In 0xd/0/eax, removed the IA32_XSS bits, which aren't relevant for XCR0.
- For 0xd/1/ecx, enumerate the IA32_XSS bits instead of a hex bitmask.
- For 0xd, added IA32_XSS PASID state (couple places).
- Renamed 0x1a: Native Model ID.
- Added synth & uarch decoding for (0,6),(11,15) Raptor Lake from
  MSR_CPUID_table.
- Added synth decoding for (0,6),(9,7),5 Pentium Gold G7400, based on
  instlatx64 sample.
- Added rudimentary synth decoding for future (0,6),(12,15) Emerald
  Rapids CPUs.
- Added 7/1/eax LASS: linear address space separation.
- Corrected 0x18/n/edx maximum number of addressible IDs, which should
  use minus-one notation.
- Certain leaves cannot be displayed correctly in isolation, i.e.
  without information about other leaves saved in the stash. For
  example, the display for leaf 3 uses bits saved from leaf 1. If the
  -l/--leaf option is used to restrict cpuid to reading only a single
  leaf, such leaves now are displayed as raw hex, rather than with
  incorrect information. This is handled by passing a NULL stash to
  print_reg() and below, and by many new checks for a NULL stash.
- Updated cache associativity strings used in 0x80000006 and 0x80000019
  leaves to use value ranges, as in AMD docs.
- Fixed mistake in AMD L3 range reservation support: it's in
  0x80000020/0 register EBX, not ECX.
- Added 0x80000026/0/edx extended APIC ID.
- Added synth & uarch decoding for (10,15),(1,1) Genoa, from AMD 57095
  revision guide.
- cpuid.man: Added AMD 57095 revision guides, and some older guides.


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