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From: Marco Atzeri <marco DOT atzeri AT gmail DOT com>
Subject: cpuinfo cache size
To: "cygwin AT cygwin DOT com" <cygwin AT cygwin DOT com>
Message-ID: <55896193.2080307@gmail.com>
Date: Tue, 23 Jun 2015 15:39:31 +0200
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Hi Corinna,

for a porting of a math lib to cygwin we are trying to obtain
the same information of

sysconf(_SC_LEVEL1_DCACHE_SIZE)
sysconf(_SC_LEVEL2_CACHE_SIZE)
sysconf(_SC_LEVEL3_CACHE_SIZE)
sysconf(_SC_LEVEL4_CACHE_SIZE)

but of course none of them is implemented in cygwin.

The /proc/cpuinfo contains :
------------------------------------------------------------------
processor       : same 0 to 3
vendor_id       : GenuineIntel
cpu family      : 6
model           : 58
model name      : Intel(R) Core(TM) i5-3320M CPU @ 2.60GHz
stepping        : 9
cpu MHz         : 2594.000
cache size      : 256 KB
fpu             : yes
fpu_exception   : yes
cpuid level     : 13
wp              : yes
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge 
mca cmov                    pat pse36 clflush dts acpi mmx fxsr sse sse2 
ss ht tm pbe pni dtes64 monitor ds_                   cpl vmx smx est 
tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 x2apic popcnt aes xsave o 
            sxsave avx f16c rdrand lahf_lm ida arat epb xsaveopt pln pts 
dtherm fsgsbase sme                   p erms
TLB size        : 0 4K pages
clflush size    : 64
cache_alignment : 64
address sizes   : 36 bits physical, 48 bits virtual
power management:
------------------------------------------------------------------

Looking on the code it seems that for
   maxe >= 0x80000006

cache_size reported on cpuinfo is calculated using L1
and immediately after overwritten with L2 value.

--------- winsup/cygwin/fhandler_proc.cc --------------------

               if (maxe >= 0x80000005) /* L1 Cache and TLB Identifiers. */
                 {
                   uint32_t data_cache, inst_cache;
                   cpuid (&unused, &unused, &data_cache, &inst_cache,
                          0x80000005);

->                cache_size = (inst_cache >> 24) + (data_cache >> 24);
                   tlb_size = 0;
                 }
               if (maxe >= 0x80000006) /* L2 Cache and L2 TLB 
Identifiers. */
                 {
                   uint32_t tlb, l2;
                   cpuid (&unused, &tlb, &l2, &unused, 0x80000006);

->                cache_size = l2 >> 16;
                   tlb_size = ((tlb >> 16) & 0xfff) + (tlb & 0xfff);
                 }
-----------------------------------------------------------------

Should be possible to have both info available ?
Any idea how to obtain the other cache infos ?


Using a third part tool
    CPU-Z version                   1.72.1.x64
I know that my architecture should be:

Number of processors            1
Number of threads               4

Processor 0
         -- Core 0
                 -- Thread 0     0
                 -- Thread 1     1
         -- Core 1
                 -- Thread 0     2
                 -- Thread 1     3

L1 Data cache           2 x 32 KBytes, 8-way set associative, 64-byte 
line size
L1 Instruction cache    2 x 32 KBytes, 8-way set associative, 64-byte 
line size
L2 cache                2 x 256 KBytes, 8-way set associative, 64-byte 
line size
L3 cache                3 MBytes, 12-way set associative, 64-byte line size

Thanks in advance
Marco

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