Mailing-List: contact cygwin-help AT cygwin DOT com; run by ezmlm List-Subscribe: List-Archive: List-Post: List-Help: , Sender: cygwin-owner AT cygwin DOT com Mail-Followup-To: cygwin AT cygwin DOT com Delivered-To: mailing list cygwin AT cygwin DOT com Message-Id: <200305142129.h4ELTam16402@proradius03> From: Arnd Riebartsch To: cygwin AT sources DOT redhat DOT com Reply-To: arnd AT arieba DOT net Subject: Digital Design with ModelSim, Verilog, VHDL Date: Wed, 14 May 2003 16:47:19 -0500 MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="d9a97fab-ea96-4653-aa59-21649ec66ad1" --d9a97fab-ea96-4653-aa59-21649ec66ad1 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: quoted-printable Hello, Modelsim is a great simulation-tool for programming of VLSI = Asic's/FPGA's/CPLD's/SoC's. Since I was involved heavily with the use of ModelSim, I recently created a = manual, which can be used especially for self-study purposes. I would be glad, if someone could forward my link = (http://www.arieba.net/simulators.htm#ModelSim) to potential interests. Nevertheless I am also interested in open positions in Design/Verification = and/or AE positions ! Best Regards Arnd Riebartsch Phone: 469-583-2558 P.S.: Resume: http://www.cv.arieba.net --d9a97fab-ea96-4653-aa59-21649ec66ad1 Content-Type: text/plain; charset=us-ascii -- Unsubscribe info: http://cygwin.com/ml/#unsubscribe-simple Problem reports: http://cygwin.com/problems.html Documentation: http://cygwin.com/docs.html FAQ: http://cygwin.com/faq/ --d9a97fab-ea96-4653-aa59-21649ec66ad1--