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From: Achim Gratz <Stromeko@nexgo.de>
To: cygwin@cygwin.com
Subject: Re: Shares with strange ACL settings
References: <20150812155817.GN13029@calimero.vinschen.de>	<878u9g9y6b.fsf@Rainer.invalid>	<20150812183220.GO13029@calimero.vinschen.de>	<87vbck8h92.fsf@Rainer.invalid>	<20150813163302.GB28349@calimero.vinschen.de>	<20150813175302.GD28349@calimero.vinschen.de>	<20150814082959.GE28349@calimero.vinschen.de>	<loom.20150814T125223-728@post.gmane.org>	<20150814134552.GG28349@calimero.vinschen.de>	<87bne8d1tm.fsf@Rainer.invalid>	<20150815183126.GT28349@calimero.vinschen.de>
Date: Sat, 15 Aug 2015 21:04:27 +0200
In-Reply-To: <20150815183126.GT28349@calimero.vinschen.de> (Corinna Vinschen's	message of "Sat, 15 Aug 2015 20:31:26 +0200")
Message-ID: <87vbcgbcg4.fsf@Rainer.invalid>
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Corinna Vinschen writes:
>> I've also tried to find out why the L3 cache is not reported for AMD in
>> cpuinfo.  It seems the reason is that it is logically part of the
>> northbridge system, even if it is on-die and gets reported via CPUID.
>
> Ok, interesting.  Still strange, isn't it?

In any case, it's not due to an inability to get at the cache sizes.
The code that fills those in has the sizes for all levels, but the cache
size structure that gets used in /proc/cpuinfo is filled from L2 on AMD
and L3 on Intel.  If you need the full information on Linux you'd go to
/sys/devices/system/cpu or use one of the more specialized programs that
give you topology information anyway.


Regards,
Achim.
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