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From: Achim Gratz <Stromeko@nexgo.de>
To: cygwin@cygwin.com
Subject: Re: Shares with strange ACL settings
References: <20150812152601.GL13029@calimero.vinschen.de>	<loom.20150812T172703-7@post.gmane.org>	<20150812155817.GN13029@calimero.vinschen.de>	<878u9g9y6b.fsf@Rainer.invalid>	<20150812183220.GO13029@calimero.vinschen.de>	<87vbck8h92.fsf@Rainer.invalid>	<20150813163302.GB28349@calimero.vinschen.de>	<20150813175302.GD28349@calimero.vinschen.de>	<20150814082959.GE28349@calimero.vinschen.de>	<loom.20150814T125223-728@post.gmane.org>	<20150814134552.GG28349@calimero.vinschen.de>
Date: Sat, 15 Aug 2015 17:11:01 +0200
In-Reply-To: <20150814134552.GG28349@calimero.vinschen.de> (Corinna Vinschen's	message of "Fri, 14 Aug 2015 15:45:52 +0200")
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Corinna Vinschen writes:
> Btw., can you please also check /proc/cpuinfo?

The output is correct now for a SandyBridge dual-core CPU with
logical processors (aka HT) and an IvyBridge dual-core CPU w/o HT.

I've also tried to find out why the L3 cache is not reported for AMD in
cpuinfo.  It seems the reason is that it is logically part of the
northbridge system, even if it is on-die and gets reported via CPUID.


Regards,
Achim.
-- 
+<[Q+ Matrix-12 WAVE#46+305 Neuron microQkb Andromeda XTk Blofeld]>+

SD adaptation for Waldorf microQ V2.22R2:
http://Synth.Stromeko.net/Downloads.html#WaldorfSDada

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