Subject: RE: GCC untrackable crashes
From: Kevin Camera <[email-masked]>
To: "'Kevin Wright'" <[email-masked]>, Kevin Camera <[email-masked]>
Cc: "[email-masked]'" <[email-masked]>
Date: Wed, 21 Feb 2001 12:22:00 -0800

I was recommended to add more details about this problem (the seg fault
within __size_of_stack_reserve).  I was hesitant to do this because the code
seems to be pretty standard and works on all other machines.

The following are the two cases which cause the fault.  The first occurs on
the call to delete, and the second occurs on the call to outfile.close().
The second case is really long, but as you can see all I do is open up an
ofstream, pump through a bunch of data (with nothing fancy, just text), and
then try to close it.  This succeeds for the first several files, and then
for no apparent reason causes the fault.  [The same case for the first
error: the delete call works fine several times before it causes the fault]

For reference, here is what happens when it crashes:
> ****************************************************
> Program received signal SIGSEGV, Segmentation fault.
> 0x6107292d in _size_of_stack_reserve__ ()
> (gdb) bt
> #0  0x6107292d in _size_of_stack_reserve__ ()
> Cannot access memory at address 0x2000000
> ****************************************************

The examples are below.  Thanks much for the help...
Kevin
[email-masked]

************************************************************************
char* state::TopDownEntry()
{
    int length = 0;
    char *entrybuf, *tmpbuf;
    state *currentState = this;

    // Initialize entrybuf in heap space
    entrybuf = new char [1];
    strcpy(entrybuf,"");

    // Loop until we reach the chart level
    while ( currentState->parentNode != 0 ) {
	// Prepend the entry code of this level to the lower levels
	//cerr << "State " << currentState->name
	// << "\n  entry: " << currentState->entry
	// << "  previous: " << entrybuf << endl;
	if ( currentState->entry != NULL ) {
	    // Allocate a new string buffer
	    length += strlen(currentState->entry);
	    tmpbuf = new char[length];
	    // Copy in the new code and add the old at the end
	    strcpy(tmpbuf,currentState->entry);
	    strcat(tmpbuf,entrybuf);
	    // Set result to the new buffer
	    delete [] entrybuf;
	    entrybuf = tmpbuf;
	}
	currentState = states[currentState->parentNode];
    }
    return entrybuf;
}
************************************************************************
int
GenerateVHDL(char *mdlfile, char *dir)
{
    int counter, counter2, destNode;
    state *thisChart;
    state *thisState;
    datastruct *thisData;
    datastruct *thisEvent;
    transition *thisTrans;
    char *flatName;

    chartIndex = 0;
    ofstream outfile;

    while ( chartIndex < numCharts ) {

	thisChart = toplevel[chartIndex];

	// Construct path and filename and create new file
	strcpy(buf,dir);
#ifdef WIN32
	if ( buf[strlen(buf)-1] != '\\' ) strcat(buf,"\\");
#else
	if ( buf[strlen(buf)-1] != '/' ) strcat(buf,"/");
#endif
	flatName = strrchr(thisChart->name,'/');
	if ( flatName == NULL ) {
	    flatName = thisChart->name;
	} else {
	    flatName++;
	}
	strcat(buf,flatName);
	strcat(buf,".vhd");
	outfile.open(buf,ios::out|ios::trunc);

	// Make sure new file got opened
	if ( !outfile ) {
	    cerr << "Unable to create " << buf << "! Skipping file.\n";
	    chartIndex++;
	    continue;  // Proceed to next file
	}

	// Start sending VHDL
	cout << "\nGenerating VHDL code for " << thisChart->name << "...\n";
	outfile << "-- VHDL generated by sf2vhd (Berkeley Wireless Research
Center, 2000)\n"
	           "--  from Simulink/Stateflow file " << mdlfile << "\n\n";

	// Include necessary libraries
	outfile <<
	    "library IEEE;\n"
	    "use IEEE.std_logic_1164.all;\n"
	    "use IEEE.std_logic_arith.all;\n\n"
	    //"use IEEE.std_logic_unsigned.all;\n"
	    //"use IEEE.std_logic_signed.all;\n"
	    "\n";

	//
	// Begin entity block
	//
	outfile << "entity " << flatName << " is\n";

	// List the input/output data as signals in a port() block
	outfile << "\tport(";
	for ( counter = 0 ; chartData[chartIndex][counter] != NULL ;
counter++) {
	    thisData = chartData[chartIndex][counter];
	    switch (thisData->type) {
	    case INPUT:
	        outfile << "signal " << thisData->name << " : in ";
	        break;
	    case OUTPUT:
		outfile << "signal " << thisData->name << " : out ";
		break;
	    default:
		continue;
	    }
	    outfile << PrintSignalType(buf,thisData) << ";\n\t     ";
	}
	for ( counter = 0 ; chartEvents[chartIndex][counter] != NULL ;
counter++) {
	    thisEvent = chartEvents[chartIndex][counter];
	    outfile << "signal " << thisEvent->name
		    << "_PRES : in std_logic;\n\t     ";
	}
	// End of the port statements
	outfile << "signal SFRESET : in bit;\n\t     "
	           "signal BCLK : in bit);\n";

	// Define all Stateflow "library" functions
	//outfile << functiondecs;
	
	outfile << "end " << flatName << ";\n";
	//
	// End entity block
	//

	//
	// Begin architecture block
	//
	outfile << "\narchitecture behavior of " << flatName << " is\n\n";

	// Print constant data
	outfile << "\t-- Constant data\n";
	for ( counter = 0 ; chartData[chartIndex][counter] != NULL ;
counter++ ) {
	    thisData = chartData[chartIndex][counter];
	    if ( thisData->type == CONSTANT ) {
		outfile << "\tconstant " << thisData->name << "_SIG : "
 			<< PrintSignalType(buf,thisData)
			<< " := ";
		if ( thisData->bitwidth == 1 )
		    outfile << "'" << thisData->initvalue << "';\n";
		else
		    outfile << thisData->initvalue << ";\n";
	    }
	}
	outfile << endl;

	// Print signals for all data
	outfile << "\t-- Signals for all inputs, outputs, and local data\n";
	for ( counter = 0 ; chartData[chartIndex][counter] != NULL ;
counter++ ) {
	    thisData = chartData[chartIndex][counter];
	    if ( thisData->type != CONSTANT ) {
		outfile << "\tsignal " << thisData->name << "_SIG : "
			<< PrintSignalType(buf,thisData) << ";\n";
		if ( thisData->type != INPUT ) {
		    outfile  << "\tsignal " << thisData->name << "_NEXT : "
			     << PrintSignalType(buf,thisData) << ";\n";
		}
	    }
	}
	for ( counter = 0 ; chartEvents[chartIndex][counter] != NULL ;
counter++) {
	    thisEvent = chartEvents[chartIndex][counter];
	    outfile << "\tsignal " << thisEvent->name
		    << "_PRES_SIG : std_logic;\n";
	}
	outfile << "\tsignal state_SIG : integer range 0 to "
		<< numStates[chartIndex] << ";\n"
	           "\tsignal state_NEXT : integer range 0 to "
		<< numStates[chartIndex] << ";\n";

	// Begin the architecture and assign the input signals to their
ports
	outfile << "\nbegin\n\n";
	outfile << "\t-- Map all input ports to signals\n";
	for ( counter = 0 ; chartData[chartIndex][counter] != NULL ;
counter++ ) {
	    thisData = chartData[chartIndex][counter];
	    if ( thisData->type == INPUT )
		outfile << "\t" << thisData->name << "_SIG <= "
			<< thisData->name << ";\n";
	}
	for ( counter = 0 ; chartEvents[chartIndex][counter] != NULL ;
counter++) {
	    thisEvent = chartEvents[chartIndex][counter];
	    outfile << "\t" << thisEvent->name << "_PRES_SIG <= "
		    << thisEvent->name << "_PRES;\n";
	}

	// Assign the outputs to the _NEXT signals (combinational logic
outputs)
	outfile << "\n\t-- Map all output ports to logic output signals\n";
	for ( counter = 0 ; chartData[chartIndex][counter] != NULL ;
counter++ ) {
	    thisData = chartData[chartIndex][counter];
	    if ( (thisData->type == OUTPUT) )
	      outfile << "\t" << thisData->name << " <= "
		      << thisData->name << "_NEXT;\n";
	}

	// Begin the process
	outfile << "\n\tlogical : process(";
	for ( counter = 0 ; chartData[chartIndex][counter] != NULL ;
counter++ ) {
	    thisData = chartData[chartIndex][counter];
	    if ( thisData->type != CONSTANT )
		outfile << thisData->name << "_SIG,\n\t                  ";
	}
	outfile << "state_SIG,\n\t                  SFRESET)\n\n";

	// Print out all the variable names (one for every datum)
	for ( counter = 0 ; chartData[chartIndex][counter] != NULL ;
counter++ ) {
	    thisData = chartData[chartIndex][counter];
	    outfile << "\tvariable " << thisData->name << "_VAR : "
		    << PrintSignalType(buf,thisData)
		    << ";\n";
	}
	for ( counter = 0 ; chartEvents[chartIndex][counter] != NULL ;
counter++) {
	    thisEvent = chartEvents[chartIndex][counter];
	    outfile << "\tvariable " << thisEvent->name
		    << "_PRES_VAR : std_logic;\n";
	}
	outfile << "\tvariable state_VAR : integer range 0 to "
		<< numStates[chartIndex] << ";\n\n";

	// Begin the process and assign all variables to the signal value
	outfile << "\tbegin\n\n"
	           "\t\t-- Begin with all variables assigned to the latched
signal\n";
	for ( counter = 0 ; chartData[chartIndex][counter] != NULL ;
counter++ ) {
	    thisData = chartData[chartIndex][counter];
	    outfile << "\t\t" << thisData->name << "_VAR"
		    << " := " << thisData->name << "_SIG;\n";
	}
	for ( counter = 0 ; chartEvents[chartIndex][counter] != NULL ;
counter++) {
	    thisEvent = chartEvents[chartIndex][counter];
	    outfile << "\t\t" << thisEvent->name << "_PRES_VAR"
		    << " := " << thisEvent->name << "_PRES_SIG;\n";
	}
	outfile << "\t\tstate_VAR := state_SIG;\n";

	// Now the state machine case statement
	outfile << "\n\t\tcase state_SIG is\n";

	//
	// Traverse the states and generate action code for each one
	//
	for ( counter = 0; thisChart->substates[counter] != NULL; counter++
) {
	    thisState = thisChart->substates[counter];
	    thisState->GenerateStateCode(outfile);
	}
	//
	// End of state action tree
	//

	// End case statement, assign variables to signals, and end process
	outfile << "\t\t\twhen others =>\n\t\t\t\tNULL;\n"
	           "\t\tend case;\n\n";

	// Add a synchronous reset condition
	outfile << "\t\tif ( SFRESET = '0' ) then\n";
	// Set all outputs to zero by default...
	outfile << "\t\t\t-- Set outputs and local data to their initial
value\n";
	for ( counter = 0; (thisData = chartData[chartIndex][counter]) !=
NULL; counter++ ) {
	    if ( thisData->type == OUTPUT || thisData->type == LOCAL ) {
		outfile << "\t\t\t" << thisData->name << "_NEXT <= ";
		if ( thisData->bitwidth == 1 )
		    outfile << "'" << thisData->initvalue << "';\n";
		else
		    outfile << thisData->initvalue << ";\n";
// 		PrintConversionType(outfile,thisData);
// 		if ( thisData->bitwidth == 1 )
// 		    outfile << thisData->initvalue << ");\n";
// 		else
// 		    outfile << thisData->initvalue << "," <<
thisData->bitwidth << ");\n";
	    }
	}
	// ...then list the (overriding) default state and transition
actions
	outfile << "\t\t\t-- Initial transition and state entry actions\n";
	// Find the toplevel default transition and follow it down to an
initial state
	thisTrans = thisChart->deftrans;
	if ( thisTrans == NULL ) {
	    cerr << "No initial transition found into chart! Exiting...\n";
	    return 1;
	}
	else destNode =
GenerateStateDest(outfile,3,"_NEXT",thisTrans->dstNode);
	// Print the entry code for the destination and all parents
	
ParseActionCode(outfile,states[destNode]->TopDownEntry(),"_NEXT","_SIG",3);
	outfile << "\t\telse\n";

	// Assign variables to latch inputs
	outfile << "\t\t\t-- Assign logic output signals to variable
results\n";
	for ( counter = 0 ; chartData[chartIndex][counter] != NULL ;
counter++ ) {
	    thisData = chartData[chartIndex][counter];
	    if ( (thisData->type == OUTPUT) || (thisData->type == LOCAL) )
	      outfile << "\t\t\t" << thisData->name << "_NEXT <= "
		      << thisData->name << "_VAR;\n";
	}
	outfile << "\t\t\tstate_NEXT <= state_VAR;\n";
	// Close reset block
	outfile << "\t\tend if;\n\n";

	// End of the logic
	outfile << "\tend process;\n\n";

	// Print the clocking process
	outfile << "\tsynch : process(BCLK)\n\n"
	           "\tbegin\n\n"
	           "\t\tif (BCLK'EVENT and BCLK = '1') then\n\n";
	for ( counter = 0 ; chartData[chartIndex][counter] != NULL ;
counter++ ) {
	    thisData = chartData[chartIndex][counter];
	    if ( thisData->type == OUTPUT || thisData->type == LOCAL )
		outfile << "\t\t\t" << thisData->name << "_SIG <= "
			<< thisData->name << "_NEXT;\n";
	}
	outfile << "\n"
	           "\t\t\tstate_SIG <= state_NEXT;\n\n";

	outfile << "\t\tend if;\n\n"
	           "\tend process;\n\n\n";

	//
	// End architecture block
	//
	outfile << "end behavior;\n";

	// Increment the chart index and close this file -- it's done
	chartIndex++;
	outfile.close();

    } // End while ( chartIndex < numCharts )

    return 0;

}
************************************************************************

-----Original Message-----
From: Kevin Wright [mailto:[email-masked]]
Sent: Tuesday, February 20, 2001 8:14 PM
To: Kevin Camera
Subject: RE: GCC untrackable crashes

Kevin,

I think you're going to have to supply more details. Such as a test
case or some of the source.

--Kevin

> -----Original Message-----
> From: [email-masked]
> [mailto:[email-masked]]On Behalf Of Kevin Camera
> Sent: Tuesday, February 20, 2001 10:01 PM
> To: [email-masked]'
> Cc: Kevin Camera
> Subject: GCC untrackable crashes
>
>
> I have spent days on this and gotten nowhere.  If anyone can help, I would
> appreciate it greatly...
>
> I am compiling a program which compiles and runs perfectly on all versions
> of GCC on Solaris and Linux.  When I build the exact same code using the
> latest Cygwin version (and as far back as B20), the executable
> crashes with
> a seg fault.  GDB tells me this:
>
> ****************************************************
> Program received signal SIGSEGV, Segmentation fault.
> 0x6107292d in _size_of_stack_reserve__ ()
> (gdb) bt
> #0  0x6107292d in _size_of_stack_reserve__ ()
> Cannot access memory at address 0x2000000
> ****************************************************
>
> So there's not much for me to tell.  After a lot of
> single-stepping by hand,
> I noticed that it was crashing while trying to "delete" an array.
>  I traced
> all the addresses, and the memory was fine (it was created with "new" at a
> valid address).  In vain, I just removed the call to delete, and
> then I got
> the exact same crash (at a different instruction, of course),
> this time at a
> call to ofstream.close().
>
> In both cases, the fault occurred arbitrarily (there were many other
> successful calls to delete and ofstream.close, and nothing different about
> the fatal ones).  I really don't know what else to do.
>
> Thanks,
> Kevin Camera
> [email-masked]
>
> --
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>
>

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