From:	"Nick Kurshev" <nickols_k AT mail DOT ru>
To:	"pgcc AT delorie DOT com" <pgcc AT delorie DOT com>
Date:	Sun, 18 Feb 2001 19:00:21 +0000 (:)
X-Mailer:	PMMail 2.00.1500 for OS/2 Warp 4.05
MIME-Version:	1.0
Subject:	Probably pgcc-2.95.2.1 does not optimized propertly?
Message-Id:	<E14UWGo-0005df-00@mx7.port.ru>
Reply-To:	pgcc AT delorie DOT com

Hello!

I did a some test:

It is a sample of "C" source:

extern long var1,var2,var3,var4,var5;
void func( void )
{
  var1 = 0;  var2 = 0;  var3 = 0;  var4 = 0;  var5 = 0;
}

Pgcc produses following code (with -march=k6 -O9 optimization):
.file	"test.c"
gcc2_compiled.:
___gnu_compiled_c:
.text
.globl _func
_func:
	movl $0,_var1
	movl $0,_var2
	movl $0,_var3
	movl $0,_var4
	movl $0,_var5
	ret
Similar code was produced after executing "gcc -c -march=k6 -O2" and after "-march=i686 -O2".
But when architecture was unspecified (i.e. "gcc -S -c -O9 test.c"), resulting code was:

.file	"test.c"
gcc2_compiled.:
___gnu_compiled_c:
.text
.globl _func
_func:
	xorl %edx,%edx
	movl %edx,_var1
	movl %edx,_var2
	movl %edx,_var3
	movl %edx,_var4
	movl %edx,_var5
	ret

But code which is produced in last case probably will be executed much faster of first (and it is smaller). 
Because:
AMD manual "Application Note AMD-K6 MMX Enhanced Processor x86 Code Optimization. Publication 
#21828" says:
 Avoid long instruction length Use x86 instructions that are
 less than eight bytes in length. An x86 instruction that is longer
 than seven bytes cannot be short-decoded.

But it is truth - there is:
Clear registers using MOV reg, 0 instead of XOR reg, reg

Also "Intel Architecture Software Developer's Manual Volume 3: System Programming" Order Number 243190 
says:

14.8. INSTRUCTION LENGTH
...
In addition, the P6 family processors can only decode one instruction at a time when an instruction
is longer than 7 bytes.
...  

What you think about?

Best regards! Nick

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