Mail Archives: geda-user/2018/05/08/04:52:57
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Dnia 8 maja 2018 08:06 michalwd1979 <gedau AT igor2 DOT repo DOT hu> napisa=C5=
=82(a): Very nice board! I see a few oddities. I ask about them to unde=
rstand your use case better and to make sure these are not .pcb import bug=
s in pcb-rnd. Thanks! I see you did an interesting RF construct (wilk=
inson splitter?) at RU200. With subcircuits that sort of things could be d=
one much simpler, as you don't need to use overlapping pads, just plai=
n old copper polygons. We don't yet support subcircuit-in-subcircuit, =
but that's not far away either, and then you could have R221 really be=
part of RU200. Do you have R221 as a different symbol on the schematics o=
r is it a hidden part of RU200? Would hierarchical netlists change how you=
do this? RU200 is really the un-even Wilkinson splitter. The layout of i=
t was given to me in a dxf format, so I had to create a scaled background i=
mage and=C2=A0 then draw polygons on it. Then the polygons were converted t=
o a footprint or "element" then, because the design called for no s=
oldermask on RF traces. R221 is another element in schematics (no hierarchy=
) and it is not the part of RU200, just separate component. It was done thi=
s way to help pick and place equipment - the board would be soldered by a f=
abrication company because of dense and expensive QFN components. And yes -=
the subcircuits idea would be really nice, I often wanted real tracks in f=
ootprints not just pins/pads. I am not sure about two aspects of RU200: =
it seems you have paste on these large pads that are drawn instead of poly=
gons, which looks like a bug to me. Then the mask cutout follow these pads=
closely - I have no experience with RF, but I though you'd either wan=
t a full mask cover or remove mask from the whole area of the board (as in=
a 10x15 mm rectangular mask opening over RU200). Yes it is a bug and it=
will be fixed before fabrication. The problem is lack of subcircuits in ma=
inline pcb, I wanted to have this splitter as a component (because of movin=
g/rotating), while it can not have solder paste over. I will simply remove =
this component before creating top-solderpaste gerber layer. The mask is =
also an error - thanks for pointing this out. I had this done correctly, bu=
t later with some additions and fixes the mask openings were lost, maybe wh=
en I changed clearances by mistake..... For testing it is not important but=
I need to fix it now :-). The design is to have mask clearance the same as=
pad-to-polygon clearance. I see some strange layers in the file, layer=
s called "bottom solder mask" and "top solder mask". These=
are after the silk layers, which looks to me as violation of the old form=
at that required silks to be the last two layers. These layers are also no=
t part of the layer groups. Is this some special feature of Peter's br=
anch? =C2=A0Strange, because neither the FileVersion nor the pcb release c=
omment suggests the file format is different. It seems pcb-4.0.0 ignores t=
hese layers. (Btw, in pcb-rnd we have editable mask and paste layers and m=
ask, paste, silk can feature both positively and negatively drawn objects =
so if you used these layers to draw mask cutouts, that can be done. They a=
re less hackish in pcb-rnd: they are explicit part of the layer stackup). =
I only recently find out that mainline pcb ignores "top/bottom solder=
mask", so it must be local to Peter's opengl version. The layers a=
re additional openings in soldermask, on top and bottom. Here it was needed=
because the board would be placed in a metal box, that also separates modu=
les by large "screens" - typical for RF. The screens should connect=
directly to GND. With opengl pcb editing is done in "negative" (=
You draw openings) and it is quite straight-forward. I don't know how m=
uch code complication lays under this feature.=C2=A0 I see your vias. A=
lot of them. (As expected.) Must have been fun to place them. I plan to a=
dd a feature in pcb-rnd (don't yet know when): extended objects. It wi=
ll be able to do a lot of things, from plugins, but one of the first examp=
les I want to do is a "line of vias". It would behave like a line,=
you would be able to edit it like a line, grab the endpoints, grab the wh=
ole line, copy or delete it at once; but on the board it would place a lin=
e of evenly spaced vias. I guess that'd speed up drawing wave guides o=
r those vias around the edge of your board. Would such a feature make your=
life easier? As for vias that was a bit boring but not to much... The vi=
as are the last thing placed on the pcb so I had a nice felling of work-end=
ing-soon when placing them :-). I thing that via-lines would be really us=
eful only if the vias would be configurable in some way: connect using ther=
mal X to polygon Y, with clearance Z or something. For example You create a=
via with all the specification needed and then "extend" it to a vi=
a-line. Was that Yours idea? If yes then I would really like it. Best Rega=
rds, Michael Widlok=0D
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<div><br></div><div class=3D"nh_extra"><p>Dnia 8 maja 2018 08:06 michalwd19=
79 <gedau AT igor2 DOT repo DOT hu> napisa=C5=82(a):<br></p><blockquote class=3D=
"nh_quote" style=3D"border-left: 2px solid #999; padding-left: 8px; margin:=
0;"><div id=3D"gwp471e373d"><div><br></div><div>Very nice board!<br></div>=
<div><br></div><div>I see a few oddities. I ask about them to understand yo=
ur use case better<br></div><div>and to make sure these are not .pcb import=
bugs in pcb-rnd.<br></div></div></blockquote></div><div><br></div><div>Tha=
nks! <br></div><div><br></div><div class=3D"nh_extra"><blockquote class=3D"=
nh_quote" style=3D"border-left: 2px solid #999; padding-left: 8px; margin: =
0;"><div id=3D"gwp471e373d"><div><br></div><div>I see you did an interestin=
g RF construct (wilkinson splitter?) at RU200.<br></div><div>With subcircui=
ts that sort of things could be done much simpler, as you<br></div><div>don=
't need to use overlapping pads, just plain old copper polygons. We<br></di=
v><div>don't yet support subcircuit-in-subcircuit, but that's not far away<=
br></div><div>either, and then you could have R221 really be part of RU200.=
Do you have<br></div><div>R221 as a different symbol on the schematics or =
is it a hidden part of<br></div><div>RU200? Would hierarchical netlists cha=
nge how you do this?<br></div></div></blockquote></div><div><br></div><div>=
RU200 is really the un-even Wilkinson splitter. The layout of it was given =
to me in a dxf format, so I had to create a scaled background image and&nbs=
p; then draw polygons on it. Then the polygons were converted to a footprin=
t or "element" then, because the design called for no soldermask on RF trac=
es. R221 is another element in schematics (no hierarchy) and it is not the =
part of RU200, just separate component. It was done this way to help pick a=
nd place equipment - the board would be soldered by a fabrication company b=
ecause of dense and expensive QFN components. And yes - the subcircuits ide=
a would be really nice, I often wanted real tracks in footprints not just p=
ins/pads.<br></div><div><br></div><div class=3D"nh_extra"><blockquote class=
=3D"nh_quote" style=3D"border-left: 2px solid #999; padding-left: 8px; marg=
in: 0;"><div id=3D"gwp471e373d"><div><br></div><div>I am not sure about two=
aspects of RU200: it seems you have paste on these<br></div><div>large pad=
s that are drawn instead of polygons, which looks like a bug to<br></div><d=
iv>me. Then the mask cutout follow these pads closely - I have no experienc=
e<br></div><div>with RF, but I though you'd either want a full mask cover o=
r remove mask<br></div><div>from the whole area of the board (as in a 10x15=
mm rectangular mask<br></div><div>opening over RU200).<br></div></div></bl=
ockquote></div><div><br></div><div>Yes it is a bug and it will be fixed bef=
ore fabrication. The problem is lack of subcircuits in mainline pcb, I want=
ed to have this splitter as a component (because of moving/rotating), while=
it can not have solder paste over. I will simply remove this component bef=
ore creating top-solderpaste gerber layer.<br></div><div><br></div><div>The=
mask is also an error - thanks for pointing this out. I had this done corr=
ectly, but later with some additions and fixes the mask openings were lost,=
maybe when I changed clearances by mistake..... For testing it is not impo=
rtant but I need to fix it now :-). The design is to have mask clearance th=
e same as pad-to-polygon clearance. <br></div><div><br></div><div class=3D"=
nh_extra"><blockquote class=3D"nh_quote" style=3D"border-left: 2px solid #9=
99; padding-left: 8px; margin: 0;"><div id=3D"gwp471e373d"><div><br></div><=
div>I see some strange layers in the file, layers called "bottom solder mas=
k"<br></div><div>and "top solder mask". These are after the silk layers, wh=
ich looks to me<br></div><div>as violation of the old format that required =
silks to be the last two<br></div><div>layers. These layers are also not pa=
rt of the layer groups. Is this some<br></div><div>special feature of Peter=
's branch? Strange, because neither the<br></div><div>FileVersion nor=
the pcb release comment suggests the file format is<br></div><div>differen=
t. It seems pcb-4.0.0 ignores these layers. (Btw, in pcb-rnd we<br></div><d=
iv>have editable mask and paste layers and mask, paste, silk can feature bo=
th<br></div><div>positively and negatively drawn objects so if you used the=
se layers to<br></div><div>draw mask cutouts, that can be done. They are le=
ss hackish in pcb-rnd:<br></div><div>they are explicit part of the layer st=
ackup).<br></div></div></blockquote></div><div><br></div><div>I only recent=
ly find out that mainline pcb ignores "top/bottom solder mask", so it must =
be local to Peter's opengl version. The layers are additional openings in s=
oldermask, on top and bottom. Here it was needed because the board would be=
placed in a metal box, that also separates modules by large "screens" - ty=
pical for RF. The screens should connect directly to GND. <br></div><div>Wi=
th opengl pcb editing is done in "negative" (You draw openings) and it is q=
uite straight-forward. I don't know how much code complication lays under t=
his feature. <br></div><div><br></div><div class=3D"nh_extra"><blockq=
uote class=3D"nh_quote" style=3D"border-left: 2px solid #999; padding-left:=
8px; margin: 0;"><div id=3D"gwp471e373d"><div><br></div><div>I see your vi=
as. A lot of them. (As expected.) Must have been fun to place<br></div><div=
>them. I plan to add a feature in pcb-rnd (don't yet know when): extended<b=
r></div><div>objects. It will be able to do a lot of things, from plugins, =
but one of<br></div><div>the first examples I want to do is a "line of vias=
". It would behave like<br></div><div>a line, you would be able to edit it =
like a line, grab the endpoints, grab<br></div><div>the whole line, copy or=
delete it at once; but on the board it would place<br></div><div>a line of=
evenly spaced vias. I guess that'd speed up drawing wave guides<br></div><=
div>or those vias around the edge of your board. Would such a feature make<=
br></div><div>your life easier?<br></div></div></blockquote></div><div><br>=
</div><div>As for vias that was a bit boring but not to much... The vias ar=
e the last thing placed on the pcb so I had a nice felling of work-ending-s=
oon when placing them :-). <br></div><div>I thing that via-lines would be r=
eally useful only if the vias would be configurable in some way: connect us=
ing thermal X to polygon Y, with clearance Z or something. For example You =
create a via with all the specification needed and then "extend" it to a vi=
a-line. Was that Yours idea? If yes then I would really like it.<br></div><=
div>Best Regards,<br></div><div>Michael Widlok<br></div>
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