delorie.com/archives/browse.cgi   search  
Mail Archives: geda-user/2017/04/03/00:27:14

X-Authentication-Warning: delorie.com: mail set sender to geda-user-bounces using -f
X-Recipient: geda-user AT delorie DOT com
Date: Mon, 3 Apr 2017 06:30:21 +0200 (CEST)
X-X-Sender: igor2 AT igor2priv
To: geda-user AT delorie DOT com
X-Debug: to=geda-user AT delorie DOT com from="gedau AT igor2 DOT repo DOT hu"
From: gedau AT igor2 DOT repo DOT hu
Subject: Re: [geda-user] Gnucap and Google summer of code.
In-Reply-To: <20170402235928.7143c5f4@floyd.freeelectron.net>
Message-ID: <alpine.DEB.2.00.1704030619050.27212@igor2priv>
References: <20170330125608 DOT 7d04622a AT floyd DOT freeelectron DOT net> <alpine DOT DEB DOT 2 DOT 00 DOT 1703301916570 DOT 27212 AT igor2priv> <20170402235928 DOT 7143c5f4 AT floyd DOT freeelectron DOT net>
User-Agent: Alpine 2.00 (DEB 1167 2008-08-23)
MIME-Version: 1.0
Reply-To: geda-user AT delorie DOT com
Errors-To: nobody AT delorie DOT com
X-Mailing-List: geda-user AT delorie DOT com
X-Unsubscribes-To: listserv AT delorie DOT com


On Sun, 2 Apr 2017, al davis wrote:

> On Thu, 30 Mar 2017 19:20:40 +0200 (CEST)
> gedau AT igor2 DOT repo DOT hu wrote:
>> Do you have a file format spec you'd prefer? If it's about exporting
>> geometry from pcb-rnd, it's not very hard, I am sure we could get it done
>
> The structural subset of Verilog, using these guidelines for conveying
> layout info within the format.
>
> http://gnucap.org/dokuwiki/doku.php?id=gnucap:user:netlist_import_and_export
>
> It doesn't say how to express things like stackup and vias.  Trace
> parameters like layers, thickness, width, and length are parameters to
> the "net".  If a net is not all on the same layer, the complex net can
> be encapsulated, as introduced toward the end.
>
> I know this is not enough to catch every detail.  This is the first
> one, and we need to experiment a little.
>
> The first step is to document specifically what the conversion needs to
> do, how one format is mapped to the other (and back again).

This looks like a netlist, I couldn't find a geometry description section.

From pcb-rnd we can export two things:

- geometry of the board: layers of traces, polygons, vias (the actual 
2d geometry, and _not_ parasitics, capacitance, resistance, etc. values)

- the abstract netlist we worked from; but this won't have any info about 
vias, traces, layers, materials - you just get back the input netlist that 
you have exported from the schematics editor (tinycad, kicad, gschem, 
ltspice, mentor graphics). In this setup all we do would be a netlist 
syntax conversion. We could do this, but I think it wouldn't be a big step 
forward in hooking up pcb edition with simulation.


Could you please show me an example on how your preferred format would 
express the geometry?

And the good old question remains: what software would convert the pure 
geometry to a netlist, extracting all the capacitance, resistance, etc. 
values? Or is this the part the SoC project is for?

Regards,

Igor2

- Raw text -


  webmaster     delorie software   privacy  
  Copyright © 2019   by DJ Delorie     Updated Jul 2019