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Mail Archives: geda-user/2017/02/16/13:46:15

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Date: Thu, 16 Feb 2017 19:45:04 +0100
From: "Bert Timmerman (bert DOT timmerman AT xs4all DOT nl) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>
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To: geda-user AT delorie DOT com
Subject: Re: [geda-user] RFC: edacore - should we reboot it? the EDA ecosystem
References: <alpine DOT DEB DOT 2 DOT 00 DOT 1702130818300 DOT 7286 AT igor2priv>
In-Reply-To: <alpine.DEB.2.00.1702130818300.7286@igor2priv>
Reply-To: geda-user AT delorie DOT com

gedau AT igor2 DOT repo DOT hu wrote:
> Hi all,
>
> There are things going on in pcb-rnd; emphasis slightly shifting. E.g. 
> we are much less coupled to gschem and we are less dependant on 
> gEDA/PCB file formats than we used to be. We can now communicate with 
> more and more random EDA tools. We also have some web related plans 
> with some code already implemented behind the idea.
>
> 4..5 days ago I realized these otherwise independent efforts will 
> eventually all connect up and will yield something that's in 
> considerable overlap with some of the edacore concepts - even if the 
> implementation and the path we are getting there differs from edacore's.
>
> I've written 3 writeups on the topic. I am interested in your opinion 
> especially on the higher level aspects. I know they are long, but 
> please DO READ THEM ALL, from top to bottom, before commenting in this 
> thread. Please try to describe your ideas in relation to what's 
> written in these docs instead of just throwing in random aspects. 
> Please state if you are also willing to contribute, and if so, in what 
> way, to what extent.
>
> Let's also try to skip the usual programming language, version 
> control, etc. flames out of it this time. Please also note that at 
> this stage, we are talking about real high level concepts - tiny 
> technical details on the bottom are not really interesting unless they 
> are examples of interference on the high level.
>
> 1. the EDA ecosystem idea:
>
> http://repo.hu/projects/pcb-rnd/devlog/20170212_ecosys.html
>
> This is already happening in pcb-rnd. In a sense it has a subtle 
> overlap with edacore, potentially implementing a similar service and 
> mechanism without depending on anything common (no common file formats 
> or libs)
>
> 2. what's the minimum we'd need to do for a working "edacore" setup:
>
> http://repo.hu/projects/pcb-rnd/devlog/20170213_edacore1.html
>
> These are just ideas, not even real plans. I honestly would like to 
> see developer and user opinions on these. I believe if we go for the 
> common minimum, we may gain better acceptance and have more chance 
> that the project gets anywhere.
>
> 3. something that I think was integral part of the original edacore 
> idea but I think should be a separate package to keep things simpler:
>
> http://repo.hu/projects/pcb-rnd/devlog/20170213_edacore2.html
>
> Again, just ideas, not even real plans. I'm especially interested in 
> user opinions on this.
>
> Regards,
>
> Igor2
>
Hi Igor2,

Life is busy, day job and private matters kept me away from replying 
earlier ... I hope you can see reason in that ... not everything is done 
overnight.

I read "The FOS EDA eco-system and pcb-rnd in it" write-up just now.

One thing I note is the metaphor of "bridges" between islands.

A nice one ... please note that by building bridges the island 
themselves change very little ..  at most bridge heads are founded on 
the shores and the rest is hovering above water ... life goes on on 
islands ... people enter, people leave ... please do not expect that 
islands and landmasses will shift and form a new Pangea overnight ... I 
assume that this is where the "bridge" analogy ends.

I'm all for building bridges and bridge heads on the pcb island.


Lack of time (busy day job, private matters) has prevented me from 
starting on coding a verilog importer/exporter for pcb according the 
model presented by Albert Davis during his FOSDEM 2016 talk, a very 
good, concise and inspiring presentation 
(https://archive.fosdem.org/2016/schedule/event/eda_data_interchange/), 
we had a very short recap this year unfortunately ... I think this is a 
very nice "bridge" to have.


The only addition I have to this write-up is about "Standardization": if 
we state that a certain (file) format is compliant with a (defacto) 
standard (for instance DXF, Verilog, HTML, VRML, STEP, etc.) it should 
be, it's *not* one of the things "We are not REQUIRED to do" ... yes we 
are required to do so, users depend on it, we can't do "almost" here ... 
and I really want the gcode bugs in pcb squashed ... lack of free cycles 
is preventing me ... I have to dig into gcode first, before I can tweak 
the exporter.


Onto reading the next write-up.

With kind regards and my respect for trying to build bridges,

Bert Timmerman.


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