Mail Archives: geda-user/2016/03/13/17:59:13

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To: geda-user AT delorie DOT com
From: "Simon P (simon DOT git AT le-huit DOT fr) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>
Subject: [geda-user] [vhd2vl] bug: array types, array init, '-', when others.
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Cc: larry AT doolittle DOT boa DOT org
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Date: Sun, 13 Mar 2016 22:52:59 +0100
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Reply-To: geda-user AT delorie DOT com


I try to convert some vhdl and I identify bugs and few fixes in vhd2vl.
I use vhd2vl 2.5 from github. Because I am not a lex/yacc or verilog
developer: carefully get my fixes. More precisely I don't understand
when returned values should be free in the yacc file.

All declarations before an array type declarations are forgotten:
  fix proposition:

vhd2vl does't support initialisation of memory at declaration. But it is
possible to create "initial" verilog block for initialising arrays at
  fix proposition:

I identify maybe another bug: In vhdl, a signal can have an initial
value at the declaration. The generated initialisation for registers
(bit vectors for example) is good. But wires with initial values in the
vhdl code have also initial values in verilog. With the synthesis tool
that I use (yosys), this initial value is considered like a driver and
overwrite futur drive in the architecture body. I don't know if yosys
badly interpret verilog or if this generated verilog is wrong. A bug fix
could be: delete initial value of wires. But I think that if one bit of
a bitvector has not driver in the architecture body, then the initial
value of this bit becomes a driver.

vhdl2vl doesn't support "when others=>" vhdl feature when it is mixed
with others assignation, for example:
  a<=(1=>'0',6=>'0',when others=>'1');

vhd2vl doesn't support the '-' std_logic character. But I don't know if
it exists a verilog equivalent. Maybe it is possible to treat it like a

vhd2vl doesn't support to have comments in the sensitivity list of a

vhd2vl is a very useful tool. Thanks for it.

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